Selective TLB Purging Using Memory Marking Indicators
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Solution Overview
Problem
In computing environments with virtualization technology, the process of purging translation look-aside buffer (TLB) entries is inefficient, leading to performance losses due to the need to rewalk address translation tables.
Innovation Solution
A method is introduced to selectively purge TLB entries by determining if a block of memory is backing an address translation structure, using indicators in page table entries, page status table entries, or storage keys to identify and increment counters for targeted purging, thereby improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TLB entries are purged to free memory space, then memory availability is improved, but translation speed deteriorates due to required rewalk of address translation tables
Solution Approach 1:
The patent segments the TLB into multiple sets or groups, allowing selective purging of specific segments while preserving others. This enables the system to free memory space in targeted segments without requiring complete TLB invalidation, thus maintaining translation speed for entries in preserved segments.
Solution Approach 2:
The patent implements different quality states for different TLB entries by tracking which entries are currently valid and which can be purged. This local differentiation allows the system to maintain high translation speed for active entries while freeing memory space by purging only the appropriate local segments.
2Manufacturing precision
If address translation tables are rewalked to recreate purged TLB entries, then memory management accuracy is improved, but time consumption increases
Solution Approach 1:
The patent performs preliminary actions by pre-organizing TLB entries into manageable segments and maintaining metadata about each segment's validity state. This preliminary organization enables selective purging without requiring complete rewalks, thus maintaining memory management accuracy while reducing time consumption.
Solution Approach 2:
The patent extracts and removes only the specific TLB entries that need purging from their segments, rather than removing all entries. This selective extraction maintains the integrity and accuracy of remaining entries while minimizing the time required for purging operations.
3Quantity of substance
If all TLB entries are purged to ensure memory availability, then memory space is improved, but system performance deteriorates due to loss of cached translations
Solution Approach 1:
The patent implements dynamic TLB management where segments can be selectively purged or preserved based on current system needs. This dynamic approach allows the system to optimize between memory space availability and performance by adapting which segments are purged at any given time, rather than using a static all-or-nothing purging strategy.
Solution Approach 2:
The patent changes the parameter of TLB management from a binary state (all entries present or all purged) to a granular state where individual segments can be independently controlled. This parameter change enables fine-tuned optimization of both memory space and system performance by adjusting which specific segments are purged based on current requirements.
Data Source
AI summary
A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes a purging capability that limits the purging of translation look-aside buffers and other such structures based on the marking.