Selective TLB Purging via Memory Block Marking
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Solution Overview
Problem
In computing environments with virtualization technology, the process of purging entries from translation look-aside buffers (TLBs) can lead to performance losses due to the need to rewalk address translation tables, as existing methods often result in over-purging and inefficient management of address translation structures.
Innovation Solution
A computer program product is introduced that selectively purges entries from address translation structures by determining whether a block of memory backs an address translation structure, using indicators in page table entries, page status table entries, or storage keys to decide which entries to purge, thereby minimizing unnecessary purging and optimizing TLB performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all TLB entries are purged when a purge request is received, then memory management consistency is maintained, but performance degradation occurs due to excessive rewalking of address translation tables
Solution Approach 1:
The patent segments the TLB entries into different groups based on their association with address translation structures. Instead of treating all TLB entries uniformly, the system identifies and separates entries that are backed by address translation structures from those that are not, allowing selective purging of only the necessary subset while preserving others to maintain performance.
Solution Approach 2:
The patent applies different purging strategies to different portions of the TLB based on local characteristics. Entries associated with address translation structures receive one treatment (selective purging), while other entries receive different treatment (preservation). This localized differentiation resolves the contradiction by applying the appropriate action only where needed.
2Productivity
If TLB entries are selectively purged based on memory block analysis, then performance is improved by reducing unnecessary purges, but system complexity increases due to additional determination steps
Solution Approach 1:
The patent performs preliminary analysis of memory blocks to determine whether they back address translation structures before purge operations are executed. By pre-establishing this information through indicators in page table entries, page status table entries, or storage keys, the system avoids complex real-time decision-making during purging, thus improving performance without excessive complexity.
Solution Approach 2:
The patent introduces intermediary indicators (such as bits in page table entries, page status table entries, or storage keys) that serve as mediators between the memory management system and the TLB purge mechanism. These indicators pre-mark which memory blocks back address translation structures, allowing the purge logic to simply check the indicator rather than perform complex analysis, thus reducing complexity while maintaining selectivity.
3Measurement precision
If address translation tables are rewalked to recreate purged entries, then translation accuracy is ensured, but time consumption increases
Solution Approach 1:
The patent applies partial purging by selectively removing only those TLB entries that are backed by address translation structures, rather than purging all entries. This partial action ensures that translations remain accurate for preserved entries (avoiding unnecessary rewalks) while still maintaining consistency for purged entries, thus reducing overall time loss without sacrificing accuracy.
Data Source
AI summary
A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes a purging capability that limits the purging of translation look-aside buffers and other such structures based on the marking.