TLB Resource Sharing Across Idle Cores to Reduce Miss Rates
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Solution Overview
Problem
In multi-core processors, the limited storage capacity of translation lookaside buffers (TLBs) leads to increased TLB miss rates, causing delays and performance losses as the system handles growing program workloads, as existing methods fail to efficiently manage TLB entries and reduce miss rates.
Innovation Solution
A method is introduced where a core with a full TLB queries and identifies an idle core to share TLB resources, replacing entries to expand its capacity, thereby reducing TLB miss rates and accelerating program execution by directly accessing shared TLB entries without involving the operating system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the TLB storage capacity is increased to reduce TLB miss rates, then the program execution efficiency is improved, but the device complexity and resource allocation difficulty increase
Solution Approach 1:
The patent merges TLB resources across multiple processor cores by allowing idle cores to share their TLB capacity with active cores. This combination of TLB resources effectively increases the available translation buffer capacity without requiring each core to have a larger individual TLB, thereby reducing TLB miss rates while avoiding the complexity of expanding each core's dedicated TLB storage.
Solution Approach 2:
The patent enables idle processor cores to serve a dual function: their primary processing function when active, and their TLB storage function when idle. This multi-functionality allows the system to utilize existing core resources for TLB capacity expansion without adding dedicated TLB storage components, thus improving program execution efficiency while minimizing additional device complexity.
2Adaptability or versatility
If TLB entries are replaced to accommodate new translations, then the TLB capacity utilization is improved, but the TLB miss rate increases
Solution Approach 1:
The patent introduces idle cores as intermediary storage resources between active cores and main memory. When an active core needs to replace a TLB entry, the evicted entry can be stored in an idle core's TLB instead of being lost, acting as an intermediary buffer. This allows the active core to maintain high capacity utilization while the idle core preserves the replaced entries, reducing subsequent TLB misses when those entries are needed again.
Solution Approach 2:
The patent implements a mechanism where TLB entries are temporarily discarded from active cores when space is needed, but then recovered by transferring them to idle cores' TLBs. This discarding and recovering process allows active cores to maintain optimal entry counts for current workloads while preserving access to previously used translations through idle cores, thereby balancing capacity utilization with miss rate reduction.
3Measurement precision
If TLB entries are obtained from memory through operating system processing, then the translation accuracy is improved, but the access delay increases
Solution Approach 1:
The patent applies preliminary action by pre-loading TLB entries into idle cores before they are needed by active cores. When an active core experiences a TLB miss, the required entry can be quickly retrieved from an idle core's TLB rather than requiring full operating system intervention and memory access. This preliminary positioning of translation entries in idle cores significantly reduces the time penalty for address translation while maintaining accurate translations.
Solution Approach 2:
The patent uses copying by duplicating TLB entries from active cores to idle cores. When an active core has a valid TLB entry, it can be copied to an idle core's TLB for future use. This copying mechanism allows the system to maintain accurate address translations in multiple locations, enabling fast retrieval without requiring repeated operating system processing or memory accesses, thus reducing translation delay while preserving accuracy.
Data Source
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AI summary
A translation lookaside buffer TLB management method and a multi-core processor are provided. The method is applied to the multi-core processor, the multi-core processor includes a first core, the first core includes a TLB, and the method includes: receiving, by the first core, a first address translation request, and querying the TLB of the first core based on the first address translation request (210); determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry (220); when determining that entry storage in the TLB of the first core is full, determining a second core from cores in an idle state in the multi-core processor (230); and replacing a first entry in the TLB of the first core with the first target TLB entry, and storing the first entry in a TLB of the second core (240). According to this method, a TLB resource of a core in an idle state is used to expand a TLB capacity of a working core, thereby reducing a TLB miss rate and accelerating program execution.