TLB Snooping Mechanism for Memory Coherency in Multi-Node Systems
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Solution Overview
Problem
Multiple-node computing systems face performance penalties due to the Modified-Exclusive-Shared-Invalidated (MESI) coherency protocol and the need for additional hardware in directory-based coherency protocols, making them unsuitable for cost-constrained applications like embedded systems.
Innovation Solution
Implementing a translation lookaside buffer (TLB) snooping mechanism that filters inbound and outbound memory access requests based on system-wide memory addresses and shared-memory page flags, reducing the need for costly hardware and minimizing coherent transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MESI coherency protocol is used to maintain cache coherency in multiple-node systems, then memory coherency is maintained, but system performance deteriorates due to broadcast overhead for all read requests to invalidated addresses
Solution Approach 1:
The patent segments the coherency protocol into two distinct protocols: a directory-based protocol for write-related requests and a broadcast protocol for read-related requests. This segmentation allows each protocol to be optimized for its specific function, reducing the performance penalty associated with using a single protocol for all operations.
Solution Approach 2:
The patent dynamically selects the appropriate coherency protocol based on the type of memory access request. Read-related requests use the broadcast protocol, while write-related requests use the directory-based protocol. This dynamic adaptation allows the system to optimize performance for each request type while maintaining coherency.
2Productivity
If directory-based coherency protocols are employed to improve performance, then system performance improves, but hardware cost increases due to additional hardware requirements
Solution Approach 1:
The patent applies directory-based coherency only partially, specifically for write-related requests, rather than implementing it system-wide for all requests. This partial application reduces the hardware complexity and cost while still achieving performance improvements for the critical write operations.
Solution Approach 2:
The patent implements different coherency mechanisms in different parts of the system: directory-based coherency is used at nodes that generate write requests, while broadcast coherency is used for read requests. This local differentiation allows the system to optimize for performance where needed while minimizing hardware overhead elsewhere.
3Reliability
If all inbound memory access requests are handled by the cache to ensure coherency, then memory coherency is maintained, but cache performance deteriorates due to handling requests from other nodes
Solution Approach 1:
The patent introduces the translation lookaside buffer (TLB) as an intermediary between the cache and inbound memory access requests. The TLB snoop mechanism filters requests before they reach the cache, allowing the cache to focus on handling only the requests it needs to process while maintaining coherency through TLB involvement.
Solution Approach 2:
The patent extracts the coherency checking function from the cache and places it in the TLB snoop mechanism. This extraction allows the cache to handle only its primary function of data storage and retrieval, while the TLB handles the coherency checking for inbound requests, improving overall system performance.
Data Source
AI summary
A node of a multiple-node system includes a translation lookaside buffer (TLB), a cache, and a TLB snoop mechanism. The node shares memory with other nodes of the multiple-node systems, and is connected with the other nodes via a bus. The TLB snooping mechanism snoops inbound memory access requests and/or outbound memory access requests. Inbound requests are received from over the bus and are intended for the cache. However, the cache receives only the inbound requests that relate to memory addresses having associated entries within the TLB. Outbound requests are received from within the node and are intended for transmission over the bus. However, the bus coherently transmits only the outbound requests that relate to memory addresses that are part of memory pages having set shared-memory page memory flags. All other outbound memory access requests are sent over the bus non-coherently.