Translation Lookaside Buffer Switch Bank for CPU Memory Access
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Solution Overview
Problem
The dynamic mapping of virtual memory addresses to physical memory addresses using a translation lookaside buffer (TLB) is a limiting factor for CPU processing speed, especially when multiple processes share a single processor, requiring frequent flushing and reloading of TLBs, which can lead to inefficiencies in memory access.
Innovation Solution
Deploying a plurality of TLBs for each processing core, dynamically assigning them to processes with high utilization, and using a switch bank with switches that store process identifiers to connect the memory management unit to the appropriate TLB, including an additional shared TLB for processes without dedicated TLBs, thereby optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single TLB is shared among multiple processes, then device complexity is reduced, but processing speed deteriorates due to frequent flushing and reloading
Solution Approach 1:
The patent divides a single shared TLB into multiple dedicated TLBs, with each TLB assigned to a specific process. This segmentation eliminates the need for frequent flushing and reloading when switching between processes, thereby improving CPU processing speed while maintaining manageable complexity through organized process-TLB mapping via switches.
2Speed
If multiple dedicated TLBs are assigned to different processes, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent introduces switches as intermediary components that manage the mapping between processes and their dedicated TLBs. Each switch contains a register storing a process identifier, and the switch bank routes memory access requests to the appropriate TLB based on process identification. This intermediary layer simplifies the overall system architecture by providing automated process-TLB mapping, reducing the complexity burden that would otherwise result from managing multiple dedicated TLBs.
3Quantity of substance
If TLB size is increased to map more virtual memory, then memory mapping capacity is improved, but access time increases due to longer scan time
Solution Approach 1:
The patent segments the virtual address space mapping across multiple dedicated TLBs, each handling a specific process's virtual memory. This segmentation allows each TLB to maintain a manageable size optimized for fast access, while the collective capacity of all TLBs provides comprehensive virtual memory mapping capability. The switch bank enables efficient routing to the appropriate TLB based on process identifier, preventing access time penalties.
4Loss of time
If TLB size is reduced to decrease access time, then access speed is improved, but memory mapping capacity is reduced
Solution Approach 1:
The patent combines multiple small dedicated TLBs into a unified memory mapping system. Each individual TLB maintains a reduced size optimized for fast access, but the aggregate capacity of all TLBs in the bank provides comprehensive virtual memory mapping. The switch bank merges the access paths to these distributed TLBs, creating a unified system that achieves both fast access times and large total mapping capacity.
Data Source
AI summary
Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a memory management unit. Each of the translation lookaside buffers may be assigned to a different process of the processor, each of the plurality of switches may include a register for storing a different process identifier, and each of the plurality of switches may be associated with a different one of the translation lookaside buffer buffers. The memory management unit may be for receiving a virtual memory address and a process identifier from the processor and forwarding the process identifier to the plurality of switches. Each of the plurality of switches may be for connecting the memory management unit to a translation associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch.