Hierarchical TLB Unified Entry Format for Mixed Translation Schemes
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Solution Overview
Problem
Existing computer systems face inefficiencies in translation lookaside buffers (TLBs) due to the need to support both hashed page tables and tree structured page tables simultaneously, leading to decreased TLB efficiency as they can only use a part of the TLB at a time.
Innovation Solution
A computer system with a hierarchical TLB configuration comprising multiple arrays that determine whether to use a hashed page table or a hierarchical page table based on address portions, allowing for efficient caching and translation of virtual addresses to physical addresses by analyzing bit values and page sizes, thereby optimizing TLB usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the TLB is divided into two sets to support both HPT and Radix translation schemes, then both translation schemes can be supported concurrently, but the TLB efficiency decreases because each thread can only use a part of the TLB at a time
Solution Approach 1:
The patent implements a universal TLB structure that can handle both HPT and Radix translation schemes without physical partitioning. The TLB uses a unified entry format with mode indicator bits that allow it to interpret and store translations from either scheme, making the same hardware resource serve multiple functions simultaneously for different thread types
Solution Approach 2:
The patent changes the interpretation parameters of TLB entries based on the translation mode. By using mode indicator bits and selectively masking or interpreting specific fields (such as treating certain bits as valid only in HPT mode or Radix mode), the system dynamically adjusts how TLB entries are read and written, allowing full TLB utilization for both translation schemes without physical division
2Productivity
If conventional hardware mechanisms are used to load translations in the TLB automatically, then translation performance improves, but the hardware complexity and cost increase
Solution Approach 1:
The patent merges the HPT and Radix translation handling into a single unified TLB structure with combined control logic. Instead of implementing separate hardware loading mechanisms for each translation scheme, the system uses a single integrated approach where the TLB can be loaded with entries from either scheme based on the current translation mode, reducing overall hardware complexity while maintaining performance
Solution Approach 2:
The TLB is designed to automatically detect and handle the appropriate translation scheme through mode indicator bits and self-configuring behavior. The hardware mechanism adapts its operation based on the translation mode without requiring complex external control, allowing the TLB to serve itself by interpreting entries according to the active translation scheme
Data Source
AI summary
A computer system includes a translation lookaside buffer (TLB) data cache and a processor. The TLB data cache includes a hierarchical configuration comprising a first TLB array, a second TLB array, a third TLB array, and a fourth TLB array. The processor is configured to receive a first address for translation to a second address, and determine whether translation should be performed using a hierarchical page table or a hashed page table. The processor also determines (using a first portion of the first address) whether the first array stores a mapping of the first portion of the first address in response to determining that the translation should be performed using the hashed page table, and retrieving the second address from the third TLB array or the fourth TLB array in response to determining that the first TLB array stores the mapping of the first portion of the first address.