TLB Valid Bit Reuse for Fault Handling Area Reduction
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Solution Overview
Problem
Current data processing systems face high area overhead in controlling transactions following faults due to the need for duplicate information in cache and control circuitry, which is expensive and inefficient.
Innovation Solution
The system uses cache management circuitry to identify faulting transactions and set valid bits or stall indicators within the cache to invalidate or mark entries, reducing the need for additional indicator bits and minimizing area overhead, while also utilizing a control register to store previous context fault indicators for appropriate action.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If indicator bits are stored in TLB entries to track faulting transactions, then transaction control is improved, but area overhead increases
Solution Approach 1:
The patent applies multi-functionality by making the valid bit serve dual purposes: it indicates both the validity of the TLB entry and the fault status of the transaction. When a fault occurs, the valid bit is set to indicate the fault condition, eliminating the need for separate indicator bits while maintaining reliable transaction control.
Solution Approach 2:
The patent merges the fault indication function with the existing valid bit in TLB entries. Instead of adding separate indicator bits for fault tracking, the system combines the fault status information into the valid bit, thereby reducing the total area required in the TLB while maintaining the ability to control transactions following faults.
2Reliability
If duplicate fault information is stored in both control circuitry and cache, then fault handling reliability is improved, but area overhead increases
Solution Approach 1:
The patent makes the valid bit in cache entries serve multiple functions: it indicates both whether the entry is valid and whether a fault has occurred. This multi-functionality eliminates the need for duplicate fault information storage in the cache, reducing area overhead while maintaining reliable fault handling through the control register.
Solution Approach 2:
The patent extracts the fault indication function from the cache entry structure and places it in the control register. By taking out the need for duplicate fault information storage in the cache and relying on the control register instead, the system reduces cache area overhead while maintaining fault handling reliability through the valid bit's dual purpose.
Data Source
AI summary
A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.