TLB and Way Table Merging for Cache Energy Reduction
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Solution Overview
Problem
Current data processing systems with translation lookaside buffers (TLBs) face inefficiencies in cache access energy consumption due to separate address translations and cache searches, particularly in systems with physically indexed or tagged caches.
Innovation Solution
A data processing apparatus is designed with a cache and a TLB, where a way table stores way information for each memory page, allowing simultaneous access and reducing energy consumption by reusing TLB searches for both TLB and way table entries, and incorporating validity information for cache management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate address translation and cache search are performed in systems with physically indexed or tagged caches, then accurate data access is achieved, but energy consumption increases
Solution Approach 1:
The patent combines the TLB and way table into a unified structure where a single virtual address input simultaneously triggers both address translation and way determination. The TLB provides physical address translation while the way table provides cache way identification, both using the same virtual address as input and operating in parallel to eliminate redundant access operations.
Solution Approach 2:
The way table is pre-populated with way information for each virtual page, allowing the system to determine cache ways in advance before actual data access occurs. This preliminary determination of cache ways based on virtual addresses enables the cache to be efficiently configured ahead of time, avoiding dynamic searching during critical data access paths.
2Loss of time
If separate TLB and way table searches are performed, then complete address translation and way determination are achieved, but access time increases
Solution Approach 1:
The patent merges the TLB and way table operations into a single unified access mechanism. Both structures receive the same virtual address input simultaneously and provide their results (physical address and cache way) in parallel, reducing the total access time from sequential operations to a single combined operation.
Solution Approach 2:
The unified TLB-way table structure serves multiple functions simultaneously: it performs address translation, determines cache ways, and provides both pieces of information from a single access operation. This multi-functionality eliminates the need for separate dedicated search operations for each function.
3Measurement precision
If way information is stored for each memory location, then precise cache way identification is achieved, but storage requirements increase
Solution Approach 1:
The patent segments the storage structure by organizing way information at the virtual page level rather than individual memory location level. Each way table entry corresponds to a virtual page and contains way information for all memory locations within that page, reducing redundancy while maintaining precise way identification for each location through shared page-level metadata.
Data Source
AI summary
A data processing apparatus has a cache and a translation look aside buffer (TLB). A way table is provided for identifying which of a plurality of cache ways stores require data. Each way table entry corresponds to one of the TLB entries of the TLB and identifies, for each memory location of the page associated with the corresponding TLB entry, which cache way stores the data associated with that memory location. Also, the cache may be capable of servicing M access requests in the same processing cycle. An arbiter may select pending access requests for servicing by the cache in a way that ensures that the selected pending access requests specify a maximum of N different virtual page addresses, where N<M.