TLC NAND Flash Memory Data Writing Method for Speed and Reliability

Solution Overview

Problem

TLC NAND flash memory modules face challenges in increasing programming speed and reliability due to their multi-page programming mode, which results in shorter lifespan and slower data writing compared to single-page mode.

Innovation Solution

A data writing method that groups physical erasing units into two areas, where the number of data bits stored in each memory cell is less in the second area, allowing for efficient data distribution and management by determining whether to write data directly into the first area or the second area based on the number of programmed physical programming units, thereby optimizing the use of both areas for improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-page programming mode is used in TLC NAND flash memory, then storage capacity is improved, but programming speed and reliability deteriorate

Engineering Contradiction:

Improvestorage capacityVSAvoidprogramming speed

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments physical erasing units into two distinct areas: a first area for single-page programming operations and a second area for multi-page programming operations. This segmentation allows the system to choose the appropriate programming mode based on current needs, thereby maintaining high programming speed in the first area while preserving the high storage capacity capability of the second area.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic management of physical erasing units by tracking the number of programmed units and comparing it against a threshold value. When the number of programmed units exceeds the threshold, the system dynamically switches from the first area to the second area for subsequent programming operations, and vice versa. This dynamic adaptation optimizes both programming speed and storage capacity utilization based on real-time system state.

Inventive Principle:

Principle #15Dynamics

2Quantity of substance

If multi-page programming mode is used in TLC NAND flash memory, then storage capacity is improved, but reliability deteriorates

Engineering Contradiction:

Improvestorage capacityVSAvoiddata storage reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments physical erasing units into two distinct areas: a first area for single-page programming operations and a second area for multi-page programming operations. This segmentation allows the system to choose the appropriate programming mode based on current needs, thereby maintaining high programming speed in the first area while preserving the high storage capacity capability of the second area.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a threshold value as an intermediary parameter that mediates between storage capacity utilization and data reliability. By comparing the number of programmed physical erasing units against this threshold, the system can intelligently switch between programming modes, ensuring that multi-page programming (which offers higher capacity but lower reliability) is only used when necessary, thus maintaining overall system reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If single-page programming mode is used, then programming speed is improved, but storage capacity utilization deteriorates

Engineering Contradiction:

Improveprogramming speedVSAvoidstorage capacity utilization

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic management of physical erasing units by tracking the number of programmed units and comparing it against a threshold value. When the number of programmed units exceeds the threshold, the system dynamically switches from the first area to the second area for subsequent programming operations, and vice versa. This dynamic adaptation optimizes both programming speed and storage capacity utilization based on real-time system state.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of programming mode based on the system state. By monitoring the number of programmed physical erasing units and comparing it to a threshold, the system switches between single-page programming mode (for speed) and multi-page programming mode (for capacity utilization). This parameter change allows the system to adaptively optimize performance based on current storage conditions.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10283196B2Data writing method, memory control circuit unit and memory storage apparatus

Publication Date: 2019.05.07 PHISON ELECTRONICS

AI summary

A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.