TLC Data Programming With Hybrid Parity to Reduce XOR Overhead

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Solution Overview

Problem

Existing data storage technologies face challenges in reducing XOR parity overhead while maintaining or increasing the reliability of solid state drives (SSDs), leading to reduced capacity for user data due to excessive XOR parity data storage.

Innovation Solution

Implementing a first memory device with a smaller XOR element ratio and a read verify operation on a wordline or erase block basis to identify and fix program failures before programming to a second memory device, thereby reducing the need for XOR parity data in a second memory superblock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If XOR parity data is stored in each location of the data write (volatile memory cache, non-volatile memory cache, foggy program, fine program), then program failures can be corrected, but the XOR parity overhead increases and reduces over provisioning or capacity for user data

Engineering Contradiction:
Improveprogram failure correctionVSAvoidXOR parity overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent performs read verify operations after foggy programming to detect and correct program failures before fine programming occurs. By identifying and fixing errors in advance, the system reduces the amount of XOR parity data needed during fine programming, thereby decreasing overall XOR parity overhead while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent discards the need to store XOR parity data in multiple locations by recovering error correction capability through preliminary read verify operations. Instead of maintaining XOR parity throughout the entire programming sequence, the system recovers from program failures early and uses minimal XOR parity only where absolutely necessary

Inventive Principle:
Principle #34Discarding and recovering

2Reliability

If read verify operation is executed on wordline to wordline basis or erase block to erase block basis, then program failures are found and fixed prior to programming to the second memory device, but the programming process complexity increases

Engineering Contradiction:
Improveprogram failure detectionVSAvoidprogramming process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the programming process into distinct phases (foggy programming followed by fine programming) with read verify operations performed at specific segmentation points. This structured segmentation allows for systematic error detection and correction without overwhelming complexity, as each phase has a defined purpose and verification step

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12399638B2TLC data programming with hybrid parity
Publication Date: 2025.08.26 SANDISK TECHNOLOGIES LLC
  • US12399638B2 patent drawing
  • US12399638B2 patent drawing
  • US12399638B2 patent drawing

AI summary

The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.