Automated TLM to RTL Synthesis for Chip Design
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Solution Overview
Problem
The conventional conversion from high-level transaction level modeling (TLM) to register transfer level (RTL) descriptions in computer architecture design is time-consuming and error-prone, requiring manual processes and repeated translations due to design modifications during verification.
Innovation Solution
A method and system that automatically translate TLM descriptions to RTL descriptions, generating cycle-accurate or behavioral synthesis-compatible RTL code, with interface logic and signal accesses, compatible with existing technologies for embedded processors and systems-on-a-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual conversion from TLM to RTL is used, then conversion accuracy can be controlled, but conversion time and error rate increase significantly
Solution Approach 1:
The patent replaces the manual mechanical conversion process with an automated computer-based synthesis system. The TLM description is automatically parsed and converted to RTL code through software algorithms, eliminating manual typing and copying operations while maintaining accuracy through systematic transformation rules.
Solution Approach 2:
The synthesis system performs self-service by automatically generating RTL code from TLM descriptions without requiring manual intervention. The system includes built-in capabilities to parse TLM syntax, generate corresponding RTL instructions, and handle interface logic automatically, making the conversion process autonomous.
2Reliability
If manual conversion process is used, then conversion steps can be reviewed, but the process becomes error-prone and time-consuming
Solution Approach 1:
The patent replaces manual conversion with automated computer-based synthesis that systematically transforms TLM descriptions to RTL code through programmed algorithms, eliminating human errors in copying and typing while maintaining systematic review through automated validation.
Solution Approach 2:
The synthesis system incorporates feedback mechanisms where the generated RTL code can be validated against the original TLM description, and errors can be detected and corrected automatically. This feedback loop ensures reliability while maintaining high conversion efficiency.
3Adaptability or versatility
If TLM description is modified during verification, then design can be optimized, but repeated manual conversion is required increasing time consumption
Solution Approach 1:
The patent implements a dynamic synthesis system where the TLM description can be modified during verification and the RTL code is automatically regenerated. This dynamic capability allows design optimization without requiring manual reconversion, as the system adapts to changes in real-time.
Solution Approach 2:
The synthesis system maintains continuous operation where modifications to the TLM description automatically trigger regeneration of the RTL code. This continuous useful action eliminates interruptions and repeated manual conversion steps, allowing seamless design optimization.
4Productivity
If automated TLM to RTL conversion is implemented, then conversion time is reduced, but system complexity increases
Solution Approach 1:
The patent segments the synthesis system into distinct functional modules: TLM parser, code generator, interface logic generator, and validation module. This segmentation manages system complexity by dividing the automated conversion process into manageable, independent components that can be developed and maintained separately.
Data Source
AI summary
Converting from transaction level model to register transfer level. A method comprises accessing a transaction level model description. Function calls in the transaction level model description are automatically converted to signal accesses in a register transfer level description. Interlace logic is automatically generated in the register transfer level description. The interface logic provides an interface between a bus interface and the signal accesses. The register transfer level description is stored in a computer readable medium.