Transactional Memory Priority Conflict Resolution

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Solution Overview

Problem

Current Restricted Transactional Memory (RTM) implementations abort transactions randomly when data conflicts occur, leading to performance issues and live-lock situations due to the lack of thread priority differentiation, resulting in inefficient resource utilization and reduced performance.

Innovation Solution

Assigning priorities to transactional memory regions using instructions like XBEGIN with an optional priority operand or new instructions like XSTPRIO, allowing higher priority threads to continue while aborting lower priority threads upon conflicts, thereby managing cache line access and reducing retry collisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If RTM transactions abort randomly when data conflicts occur, then all threads are treated equally without priority differentiation, but this leads to performance degradation and live-lock situations due to repeated aborts and retries

Engineering Contradiction:
Improvetransaction completion reliabilityVSAvoidthread execution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a priority parameter (QoS parameter) that changes the behavior of transaction conflict resolution. Instead of random or uniform abort behavior, the system now uses the priority parameter to deterministically select which thread to abort, transforming the conflict resolution mechanism from non-discriminatory to priority-based, thereby improving both reliability and productivity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments threads into different priority levels (e.g., high priority and low priority threads). This segmentation allows the system to treat different threads differently during conflict resolution, enabling critical threads to proceed while non-critical threads are aborted, thus preventing live-lock situations and improving overall system productivity

Inventive Principle:
Principle #1Segmentation

2Productivity

If higher priority threads are allowed to complete while lower priority threads are aborted upon conflicts, then resource utilization improves and collisions reduce, but the system complexity increases due to priority management overhead

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidpriority management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The priority QoS parameter is assigned to threads in advance, before conflicts occur. This preliminary assignment eliminates the need for complex runtime priority determination logic, as the priority is already encoded in the thread's QoS parameter. The conflict resolution mechanism simply compares these pre-assigned parameters, significantly reducing the complexity overhead while maintaining high productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Each thread carries its own priority information in its QoS parameter, making the priority information self-contained and readily available for conflict resolution. The system does not need external priority management infrastructure; the threads themselves provide the necessary priority information, simplifying the overall system architecture while enabling efficient resource utilization

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10719442B2Apparatus and method for prioritized quality of service processing for transactional memory
Publication Date: 2020.07.21 INTEL CORP
  • US10719442B2 patent drawing
  • US10719442B2 patent drawing
  • US10719442B2 patent drawing

AI summary

An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.