TMBS Device Etch Stop Layers for Yield Improvement
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Solution Overview
Problem
Conventional methods for fabricating trench MOS barrier Schottky (TMBS) devices face issues with non-uniform etching, leading to over-etching and residue problems, which negatively impact the yield of these high-frequency, high-speed semiconductor devices.
Innovation Solution
The method involves forming a first and second barrier dielectric layer over the gates, with these layers serving as etch stops to protect the gate dielectric layer during the etching of the intermediate dielectric layer, reducing the risk of over-etching and residue, and allowing for more uniform etching by controlling the thickness and formation of the first barrier dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etching is used to etch the intermediate dielectric layer, then the etching process can be completed, but the etching speed is non-uniform across the reaction chamber causing thickness non-uniformity and over-etching
Solution Approach 1:
The patent applies preliminary action by forming the first barrier dielectric layer before the etching process. This layer serves as a protective buffer that compensates for the non-uniform etching, ensuring that the gate dielectric layer is not over-etched even when plasma distribution causes variability in etching speed across the reaction chamber.
Solution Approach 2:
The first barrier dielectric layer acts as a cushioning layer formed beforehand to absorb the non-uniformity of the etching process. By having this extra layer in place before etching the intermediate dielectric layer, the patent prevents direct damage to the gate dielectric layer from over-etching, thereby improving manufacturing precision without requiring shorter etching times.
2Reliability
If the intermediate dielectric layer is formed to a large thickness to ensure complete coverage, then coverage is improved, but the thickness non-uniformity increases making it difficult to etch uniformly
Solution Approach 1:
The patent segments the dielectric structure into multiple distinct layers: the gate dielectric layer, the first barrier dielectric layer, and the intermediate dielectric layer. This segmentation allows each layer to serve its specific function - the intermediate layer provides coverage while the first barrier layer provides a uniform etch stop, resolving the conflict between coverage and thickness uniformity.
Solution Approach 2:
The first barrier dielectric layer acts as an intermediary between the gate dielectric layer and the intermediate dielectric layer. It mediates the etching process by providing a uniform etch stop surface, allowing the intermediate layer to be formed with large thickness for coverage without compromising the precision of the underlying gate dielectric layer.
3Productivity
If etching time is extended to remove the thick intermediate dielectric layer completely, then complete removal is achieved, but over-etching damages the gate dielectric layer
Solution Approach 1:
The first barrier dielectric layer serves as a pre-formed cushion that protects the gate dielectric layer from over-etching damage. This allows the etching process to run for extended periods to completely remove the thick intermediate dielectric layer while the barrier layer absorbs the excess etching, maintaining the integrity of the gate dielectric layer.
Solution Approach 2:
The first barrier dielectric layer acts as an intermediary protective layer during the etching process. It mediates between the aggressive plasma etching and the sensitive gate dielectric layer, allowing complete removal of the intermediate layer while preventing damage to the underlying structure.
4Manufacturing precision
If the etching process is stopped early to prevent over-etching, then the gate dielectric layer is protected, but residue of the intermediate dielectric layer remains
Solution Approach 1:
The patent applies preliminary action by forming the first barrier dielectric layer before etching. This pre-formed layer enables the etching process to proceed to complete removal of the intermediate dielectric layer without risking damage to the gate dielectric layer, as the barrier layer is already in place to provide protection.
Solution Approach 2:
The first barrier dielectric layer serves as an intermediary that allows the etching process to go to completion. It mediates the conflict between stopping early (to protect the gate dielectric) and continuing (to remove all intermediate layer residue) by providing a sacrificial protective layer that can be fully etched away safely.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of TMBS devices by minimizing damage to the gate dielectric layer, reducing equipment performance requirements, and expanding the process window, thereby improving the uniformity and efficiency of the fabrication process.
Implementation Method 1
In step S7, the intermediate dielectric layer 50 and the hard mask layer 20 are etched by dry etching, i.e., using plasma of an etchant gas
Data Source
AI summary
A method for yield improvement of trench MOS barrier Schottky (TMBS) devices includes: forming a plurality of trenches in a substrate; forming a gate dielectric layer over a surface of the substrate and inner surfaces of the trenches; forming gates in the trenches; forming a first barrier dielectric layer, a second barrier dielectric layer and an intermediate dielectric layer over the trenches; etching the intermediate dielectric layer with the second barrier dielectric layer serving as an etch stop layer to form a window for forming contact holes; etching a portion of the second barrier dielectric layer within the window using the first barrier dielectric layer as an etch stop layer; and etching in the window to remove a portion of the first barrier dielectric layer overlying the gates and a portion of the gate dielectric layer overlying the substrate.