TMD Nanosheet Transistor Spacer-Liner Layout for Lower Capacitance
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Solution Overview
Problem
TMD nanosheet transistors face challenges with high parasitic capacitance and access resistance, particularly due to difficulties in doping source and drain regions and the use of low dielectric constant materials.
Innovation Solution
The implementation of a spacer made from low dielectric constant material above a liner to facilitate charge transfer in the source and drain regions of TMD nanosheet transistors, thereby reducing capacitance and access resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If low dielectric constant material is used for spacer, then parasitic capacitance is reduced, but access resistance increases due to difficulty in doping source and drain regions
Solution Approach 1:
The patent applies local quality by creating distinct regions with different doping concentrations within the source and drain regions. The method forms a first doped region with a first doping concentration and a second doped region with a second doping concentration, where the doping concentrations differ. This local variation in doping quality allows optimization of both capacitance and access resistance in different spatial zones of the same structure.
Solution Approach 2:
The patent utilizes parameter changes by varying the doping concentration parameter across different regions of the source and drain structures. By controlling the doping concentration to be different in the first doped region versus the second doped region, the patent optimizes electrical properties to simultaneously reduce parasitic capacitance and maintain acceptable access resistance.
2Length of moving object
If TMD material is used for channel, then transistor scaling is enabled, but doping source and drain regions becomes difficult
Solution Approach 1:
The patent applies preliminary action by forming the doped source and drain regions before completing the transistor fabrication process. The method forms first and second doped regions in the sacrificial layer prior to removing the sacrificial layer and finalizing the channel structure. This preliminary doping action enables controlled introduction of dopants into TMD material at optimal process stages.
Solution Approach 2:
The patent uses the sacrificial layer as an intermediary medium to facilitate doping of the TMD channel material. The sacrificial layer serves as a temporary substrate that allows dopant introduction and diffusion control, and is subsequently removed to reveal the final TMD-based transistor structure with properly doped source and drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic capacitance and access resistance, improving the performance of TMD nanosheet transistors by enhancing charge transport and reducing electrical insulation distances.
Implementation Method 1
a liner to transfer charge, the liner extending between the gate structure and the source structure and between the gate structure and the drain structure
Implementation Method 2
A spacer is laterally between the gate structure and the source structure and laterally between the gate structure and the drain structure
Data Source
AI summary
A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.