3D TMD Vertical Ring Transistors for Short-Channel Scaling
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, challenges arise in reducing minimum feature sizes, including the need for effective scaling of transistors while minimizing the short-channel effect and reducing contact resistance.
Innovation Solution
A three-dimensional transistor is formed using a two-dimensional semiconductor material, specifically a Transition Metal Dichalcogenide (TMD) layer on the sidewalls of a dielectric fin, with a gate stack and source/drain contact plugs designed to maximize contact area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography and planar transistor structures are used to increase integration density, then more components can be integrated into a given area, but minimum feature size reduction becomes increasingly difficult and the short-channel effect worsens
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional (3D) vertical structures. The semiconductor ring is formed on the sidewalls of dielectric fins, creating a vertical channel that extends in the third dimension. This dimensional change allows continued scaling without proportionally reducing the gate control distance, thereby maintaining manufacturing precision while increasing integration density.
Solution Approach 2:
The semiconductor material is segmented into a ring structure that wraps around the dielectric fin sidewalls. This segmentation creates multiple channel paths around the fin, effectively increasing the channel width without increasing the lateral footprint. The gate electrode is also segmented to wrap around the semiconductor ring, providing distributed control along the vertical channel.
2Productivity
If minimum channel length is reduced to increase integration density, then more transistors can be packed into a given area, but the short-channel effect increases and transistor performance deteriorates
Solution Approach 1:
By forming vertical channels on dielectric fin sidewalls, the patent extends the channel in the vertical dimension rather than relying solely on horizontal length. This allows the use of shorter horizontal channels while maintaining effective gate control through the vertical wrap-around gate structure, thereby reducing the short-channel effect while increasing density.
Solution Approach 2:
The semiconductor ring is nested around the dielectric fin, and the gate electrode is nested around the semiconductor ring. This nested configuration allows the gate to control the channel from multiple angles along the vertical channel, providing enhanced electrostatic control that suppresses the short-channel effect even with reduced channel dimensions.
3Productivity
If contact area is reduced to minimize device footprint, then integration density increases, but contact resistance increases and device performance decreases
Solution Approach 1:
The patent moves contact formation from a planar interface to a vertical sidewall interface. Source and drain contacts are formed on the vertical sidewalls of the semiconductor ring, creating extended contact areas along the vertical dimension. This vertical contact configuration increases the effective contact area without increasing the lateral device footprint, thereby reducing contact resistance while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the scaling down of minimum channel length without increasing sub-threshold swing, improving transistor performance and integration density while minimizing the short-channel effect and reducing contact resistance.
Implementation Method 1
depositing a transition metal dichalcogenide layer on the dielectric fin
Implementation Method 2
depositing a transition metal dichalcogenide layer on the dielectric fin
Implementation Method 3
performing a first anisotropic etching process on the transition metal dichalcogenide layer, wherein horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain
Data Source
AI summary
A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.