TMDS Clock Data Encoding for Bandwidth and Connector Reduction

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Solution Overview

Problem

Conventional data communication systems face limitations in maximizing bandwidth due to the need for separate channels for clock and data signals, which becomes insufficient as data communication standards evolve towards fewer connectors and higher frequency signaling.

Innovation Solution

The system combines data and clock signals using transition minimized differential signaling (TMDS) by encoding data and clock signals together and transmitting them over differential signal pairs, allowing for efficient communication through fewer channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate channels are used for clock and data signals, then synchronization is ensured, but bandwidth utilization is reduced and more connectors are required

Engineering Contradiction:
ImprovesynchronizationVSAvoidbandwidth utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines clock and data signals into a single integrated channel by encoding the clock signal within the data signal transmission. The transmitter encodes both signals together, and the receiver extracts both clock and data from the combined signal, eliminating the need for separate dedicated clock channels and improving bandwidth utilization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the data channel universal by enabling it to carry both data and clock functions simultaneously. The same transmission channel that carries data also carries the clock signal through encoding techniques, allowing a single channel to perform multiple functions that traditionally required separate channels.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate channels are used for clock and data signals, then signal integrity is maintained, but the number of connectors and channels increases

Engineering Contradiction:
Improvesignal integrityVSAvoidnumber of connectors
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock signal transmission with the data signal transmission by using the same physical channel for both. The encoder combines the clock and data signals, and the decoder separates them at the receiver end, reducing the number of required connectors and channels while maintaining signal integrity through proper encoding and decoding mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a spatial separation approach (separate physical channels for clock and data) to a temporal/signal processing approach (combining signals in the same channel but separating them through encoding/decoding). This dimensional change allows clock and data to coexist in the same physical medium without interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If traditional signaling is used, then implementation is simple, but it cannot support higher frequency signaling requirements

Engineering Contradiction:
Improveimplementation simplicityVSAvoidsignaling frequency
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent changes the signaling parameters by using differential signaling and encoded transitions instead of traditional single-ended clock signaling. The TMDS encoding scheme uses controlled voltage transitions and differential voltage levels that are optimized for high-frequency operation, enabling the system to support higher signaling frequencies while maintaining implementation feasibility through standardized encoding rules.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9230505B2Apparatus, system and method for providing clock and data signaling
Publication Date: 2016.01.05 LATTICE SEMICON CORP
  • US9230505B2 patent drawing
  • US9230505B2 patent drawing
  • US9230505B2 patent drawing

AI summary

Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal.