TMIC Synchronization for Display Black Screen Prevention

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Solution Overview

Problem

In display devices using multiple timing controller integrated circuits (TMICs), synchronization issues between TMICs lead to unnatural black screens when normal signals are not inputted or when signals deviate from the normal operational range, due to frequency deviations and mismatched signal intervals.

Innovation Solution

A driving control circuit is implemented with a master TMIC and slave TMICs, where the timing controller adjusts the end locations of data enable signals and the gate output enable signal to synchronize the data latch enable signal, ensuring proper timing and preventing errors during non-signal operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple TMICs are used to drive the display panel, then the display device can support larger and thinner designs, but frequency deviations between internal oscillators cause data output synchronization issues resulting in unnatural black screens

Engineering Contradiction:
Improvedisplay device thicknessVSAvoidimage display stability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent introduces an external clock signal as an intermediary to synchronize multiple TMICs. Instead of each TMIC using its own internal oscillator which causes frequency deviations, all TMICs receive and lock to the same external clock signal, ensuring synchronized data output and preventing unnatural black screens while maintaining the thin design enabled by multiple TMICs

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If each TMIC uses its internal oscillator for timing control, then the device structure is simplified, but frequency deviations between oscillators cause data enable signal interval mismatches leading to synchronization errors

Engineering Contradiction:
Improvetiming control structureVSAvoiddata output synchronization
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent makes the external clock signal serve as a universal timing reference for all TMICs. Instead of each TMIC having its own independent oscillator, the external clock provides a common timing basis that all TMICs use for data output, ensuring synchronized operation while keeping the overall structure relatively simple

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If the gate output enable signal timing is not adjusted, then the signal generation is straightforward, but the latch enable signal may precede the gate output enable signal causing display errors in non-signal states

Engineering Contradiction:
Improvesignal generation simplicityVSAvoiddisplay correctness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by adjusting the gate output enable signal timing in advance to ensure it occurs after the latch enable signal. This timing adjustment is made proactively to prevent the scenario where the latch enable signal would incorrectly precede the gate output enable signal, thereby avoiding display errors in non-signal states

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8698857B2Display device having a merge source driver and a timing controller
Publication Date: 2014.04.15 SILICON WORKS CO LTD
  • US8698857B2 patent drawing
  • US8698857B2 patent drawing
  • US8698857B2 patent drawing

AI summary

The present invention aims to provide a driving control circuit of a display device that is capable of preventing an unnatural black screen. To this end, the driving control circuit is configured to include a plurality of TMICs, each of which is merged with a timing controller and a source driver, and the time controller is configured to adjust end locations of the horizontal blank intervals of data enable signals to match the end locations outputted from TMICs to an end location of a horizontal blank interval of a data enable signal outputted from another TMIC, and, when a gate output enable signal is supplied, perform adjustment so as to indicate a rising edge of the gate output enable signal before the data latch enable signal having the highest frequency is supplied.