TMOS Gate Charge Reduction via Segmented P-Layer Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional TMOS devices face limitations such as high on-resistance, large gate-source and gate-drain capacitances, and high gate charge, which hinder their ability to efficiently switch large amounts of power at high frequencies, and existing improvements often degrade other device characteristics.
Innovation Solution
The introduction of a P-layer underneath the accumulation region to shield the gate electrode from the drain electrode, along with a modified doping profile, reduces Gate-Drain capacitance and enhances breakdown voltage, while maintaining low on-resistance, thereby achieving extremely low Rdson*Qg and high BVdss using standard planar technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If doping level within JFET region is increased or gate length is increased to improve on-resistance, then on-resistance is reduced, but Miller capacitance and gate charge increase and breakdown voltage decreases
Solution Approach 1:
The device is segmented into distinct regions with different doping profiles: a first doped region with higher doping concentration and a second doped region with lower doping concentration. This segmentation allows the higher doped region to contribute to lower on-resistance while the lower doped region maintains higher breakdown voltage, resolving the contradiction between these two parameters.
Solution Approach 2:
Different regions of the device are assigned different doping qualities locally. The first doped region has a first doping concentration optimized for low resistance, while the second doped region has a second doping concentration optimized for high breakdown voltage. This local differentiation allows each region to optimize its function without compromising the other.
2Reliability
If gate oxide thickness above JFET region is increased or gate length is decreased to reduce Miller capacitance and gate charge, then capacitance and charge are reduced, but on-resistance increases and threshold voltage is perturbed
Solution Approach 1:
The gate structure is segmented with respect to the doped regions, where the gate electrode extends over both the first doped region and the second doped region. This segmentation allows the gate to control the channel effectively while the differentiated doping regions manage the resistance-capacitance tradeoff independently.
Solution Approach 2:
The doping concentration varies locally under different portions of the gate electrode. The first doped region has higher doping concentration to reduce resistance where the gate control is most effective, while the second doped region has lower doping concentration to reduce capacitance and maintain breakdown voltage in the drain junction area.
3Ease of manufacture
If standard planar technology is used to simplify manufacturing, then manufacturing complexity is reduced, but achieving low figure of merit and high breakdown voltage simultaneously becomes difficult
Solution Approach 1:
The invention changes the doping concentration parameter across different regions of the device. By implementing a first doped region with one doping concentration and a second doped region with a different doping concentration using standard planar processing techniques, the device achieves improved electrical characteristics (lower figure of merit and higher breakdown voltage) without requiring complex manufacturing processes.
Data Source
AI summary
A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.