TMV Alignment Marks for Co-Planar Semiconductor Packaging

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Solution Overview

Problem

Challenges in 3-dimensional semiconductor devices include alignment and warpage issues during packaging, leading to poor solder connections and deformation, which affect integration density and performance.

Innovation Solution

The use of alignment marks with varying dimensions, specifically through-molding-vias (TMVs) of different sizes, to regulate electroplating current density and improve uniformity, enhancing positioning accuracy in pick-and-place processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If through-molding-vias (TMVs) of uniform size are used in alignment marks, then the manufacturing process is simple, but the electroplating current density is non-uniform leading to poor co-planarity and alignment precision

Engineering Contradiction:
Improvealignment precisionVSAvoidalignment mark structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by varying the dimensions of different TMVs within the alignment mark structure. Specifically, the alignment mark includes a first TMV with a first dimension and a second TMV with a second dimension that is larger than the first dimension. This non-uniform configuration creates different current density distributions during electroplating, allowing each TMV to be optimized for its specific function: the smaller first TMV provides high-precision alignment reference, while the larger second TMV ensures adequate current distribution and co-planarity. This resolves the contradiction by sacrificing structural uniformity to achieve superior alignment precision.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If smaller TMV dimensions are used for higher alignment precision, then positioning accuracy improves, but electroplating uniformity and co-planarity deteriorate

Engineering Contradiction:
Improvepositioning accuracyVSAvoidco-planarity
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent resolves this contradiction by assigning different sizes to different TMVs based on their functional requirements. The first TMV is designed with a smaller dimension (first specific dimension) to serve as the primary alignment reference, providing high positioning accuracy. The second TMV is designed with a larger dimension (second specific dimension larger than the first) to ensure adequate current density and promote uniform electroplating, thereby maintaining co-planarity. This differential sizing strategy allows the system to simultaneously achieve both high positioning accuracy and good electroplating uniformity.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If larger TMV dimensions are used to improve electroplating uniformity, then co-planarity improves, but alignment precision deteriorates

Engineering Contradiction:
Improveco-planarityVSAvoidalignment precision
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent resolves this contradiction by strategically assigning different sizes to different TMVs. The first TMV with the smaller first dimension is specifically optimized for high-precision alignment functions, while the second TMV with the larger second dimension is optimized for electroplating uniformity and co-planarity. This functional differentiation allows the alignment mark structure to simultaneously achieve both high alignment precision and good co-planarity, as each TMV size is optimized for its specific purpose rather than requiring a compromise uniform size for all TMVs.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the co-planarity of solder connections, reduces warpage, and ensures reliable interconnects, maintaining high integration density and performance in semiconductor packages.

Implementation Method 1

The first TMV and second TMV may be formed by an electroplating process

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20250349734A1Pick-and-place alignment marks for semiconductor package structures and methods of making the same
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250349734A1 patent drawing
  • US20250349734A1 patent drawing
  • US20250349734A1 patent drawing

AI summary

An embodiment semiconductor package may include a semiconductor device, a molding material laterally surrounding the semiconductor device, and an alignment mark including a first through-molding-via (TMV) and a second TMV, each formed in the molding material. The first TMV may have a first specific dimension that is between 10 microns and 150 microns and the second TMV may have a second specific dimension that is between 100 microns and 500 microns. One or more first TMVs may be located in a first region and one or more second TMVs may be located in a second region that surrounds the first region. The first region may have a diameter that is between 100 microns and 1000 microns and the second region may be an annular region having an inner diameter that is between 120 microns and 1600 microns and an outer diameter that is between 270 microns and 2000 microns.