Conductive Through Mold Vias for Fo-WLCSP Interconnect
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Solution Overview
Problem
Current semiconductor manufacturing processes for fan-out wafer level chip scale packages (Fo-WLCSPs) require complex and costly steps for forming redistribution layers, making it challenging to achieve efficient and cost-effective electrical interconnects for stackable packages.
Innovation Solution
The formation of conductive vias through a substrate and encapsulant, combined with a build-up interconnect structure using conductive through mold vias (TMVs) that are electrically connected to the substrate, allowing for a simpler and more cost-effective electrical interconnect solution for Fo-WLCSPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional redistribution layer formation processes are used for Fo-WLCSP electrical interconnect, then reliable electrical connection is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent extracts the essential function of electrical interconnection from the complex traditional RDL process and implements it through a simplified build-up interconnect structure with conductive vias formed through the encapsulant, eliminating the need for multiple lithography and etching steps while maintaining reliable electrical connection
Solution Approach 2:
Instead of forming conductive paths through planar lithography and etching steps as in traditional RDL, the patent inverts the approach by forming vertical conductive vias through the encapsulant and using build-up layers to create the interconnect structure, fundamentally changing the manufacturing paradigm
2Reliability
If traditional redistribution layer formation is used, then electrical interconnect is achieved, but manufacturing time and cost increase
Solution Approach 1:
The conductive vias are formed through the encapsulant before the build-up interconnect layers are deposited, allowing subsequent layers to be formed directly over the pre-positioned vias in a single continuous process, eliminating the need for separate alignment and patterning steps that would otherwise be required
Solution Approach 2:
The patent merges the via formation step with the encapsulant curing process by forming vias through the encapsulant after it has been deposited but before final curing, combining what would traditionally be separate manufacturing operations into one integrated step
Data Source
AI summary
A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.