Stack Packages With Through Mold Via Structures
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high density and high-speed operations while maintaining a compact form factor, requiring innovative stacking structures to enhance bandwidth and storage capacity.
Innovation Solution
The proposed solution involves a stack package configuration with multiple sub-packages, each containing semiconductor chips and through mold vias (TMVs) for connection and bypass, along with redistribution line (RDL) patterns for interconnectivity, allowing for vertical stacking and efficient electrical connections between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are vertically stacked to increase storage capacity and bandwidth, then the storage capacity and bandwidth are improved, but the manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The package structure is segmented into multiple sub-packages, each containing a semiconductor chip and associated TMVs. This segmentation allows independent processing and assembly of each sub-package, reducing overall manufacturing complexity while enabling vertical stacking to increase storage capacity.
Solution Approach 2:
The patent transitions from planar arrangement to vertical stacking by introducing through mold vias that extend through the mold compound. This dimensional change enables multiple chips to be stacked vertically, increasing storage capacity without increasing footprint area.
2Volume of moving object
If multiple semiconductor chips are vertically stacked to achieve compact form factor, then the form factor is reduced, but the alignment precision and connection reliability requirements increase
Solution Approach 1:
Through mold vias serve as intermediary connection structures between stacked semiconductor chips. These TMVs are formed through the mold compound and provide robust electrical connections that tolerate minor alignment variations, reducing the stringency of alignment precision requirements while enabling compact vertical stacking.
Solution Approach 2:
The patent changes the connection parameter from surface-mounted pads to through-mold vias that extend vertically through the package. This parameter change allows for greater tolerance in horizontal alignment while maintaining connection reliability, thereby reducing manufacturing precision requirements.
3Productivity
If through mold vias are used for connecting stacked chips, then the connection efficiency and bandwidth are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of through mold vias with the molding process itself, rather than requiring separate via formation steps. This integration combines multiple functions into a single manufacturing step, improving connection efficiency while minimizing the increase in manufacturing process complexity.
Data Source
AI summary
A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.