Stack Packages With Through Mold Vias For High Density Interconnects
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Solution Overview
Problem
There is a need for semiconductor packages with high density and high-speed operation, requiring innovative stacking structures to achieve compact form factors and increased storage capacity while maintaining efficient electrical connectivity.
Innovation Solution
The proposed solution involves a stack package configuration with multiple sub-packages stacked on a package substrate, utilizing through mold vias (TMVs) and redistribution lines (RDLs) to connect semiconductor chips to outer connectors, allowing for efficient electrical pathways and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are vertically stacked to increase storage capacity and reduce form factor, then device density and compactness are improved, but electrical connectivity and signal transmission between layers become more complex and challenging
Solution Approach 1:
The patent transitions from planar (2D) packaging to vertical (3D) stacking architecture, enabling multiple semiconductor chips to be arranged in the vertical dimension. This dimensional change increases storage capacity within a compact form factor while managing electrical connectivity through specialized inter-layer connection structures such as through-mold vias and redistribution layers that bridge signals across multiple stacking levels.
Solution Approach 2:
The patent divides the semiconductor package into multiple discrete sub-packages or stacking layers, each containing individual semiconductor chips. This segmentation allows independent fabrication and testing of each layer before assembly, simplifies the electrical connectivity management by localizing interconnections within each layer, and enables modular replacement or upgrading of specific chips without affecting the entire package.
2Reliability
If through mold vias are used to connect outer connectors to semiconductor chips through the package substrate, then electrical connectivity is improved, but manufacturing precision and alignment requirements increase
Solution Approach 1:
The patent employs preliminary action by pre-forming through-mold vias and conducting alignment markings during the mold compound packaging process, before final chip attachment. This preliminary preparation establishes precise reference positions and connection pathways in advance, enabling accurate alignment of subsequent stacking layers and reducing the complexity of high-precision alignment during final assembly.
Solution Approach 2:
The patent introduces redistribution layers (RDLs) as intermediary structures between the through-mold vias in the package substrate and the contact pads on semiconductor chips. These RDLs serve as buffer and routing layers that can compensate for minor alignment variations, redistributing electrical signals to achieve proper connectivity even when perfect alignment is not achieved, thereby reducing the stringent alignment precision requirements.
3Quantity of substance
If sub-packages are stacked on both sides of the package substrate to maximize space utilization, then storage capacity is improved, but structural stability and mechanical stress management become more challenging
Solution Approach 1:
The patent employs asymmetric stacking configuration where sub-packages are arranged differently on opposite sides of the package substrate, or where the package substrate itself has asymmetric thickness or reinforcement structures. This asymmetry allows for optimized mechanical stress distribution, compensating for the additional weight and complexity of dual-sided stacking while maintaining structural stability and preventing warpage or delamination.
Solution Approach 2:
The patent implements nested doll principle by placing additional structural support elements, such as reinforcement plates or stress-distribution layers, within the stacking architecture. These intermediate structural components are embedded between the semiconductor chips and the package substrate, providing mechanical reinforcement that enhances overall structural stability while allowing the compact dual-sided stacking configuration to be maintained.
Data Source
AI summary
A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first semiconductor chip, a first through mold via (TMV) for connection that is spaced apart from the first semiconductor chip in an X-axis direction, a first TMV for bypass that is spaced apart from the first semiconductor chip in a Y-axis direction, and a redistribution line (RDL) pattern for connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second semiconductor chip, a second TMV for connection that is spaced apart from the second semiconductor chip in the Y-axis direction, and another RDL pattern for connecting the second semiconductor chip to the second TMV for connection. The second sub-package stacked is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.