TO Package Structure With Double-Sided Cooling and EMI Shielding
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Solution Overview
Problem
Current transistor package structures face challenges with single-sided heat dissipation, limited electromagnetic interference (EMI) shielding, and unreliable heat sink installation, leading to reliability issues, especially in high-temperature and vibration environments.
Innovation Solution
A double-sided heat dissipation design using metal and ceramic substrates with a metal tab for heat sink installation, providing effective EMI shielding and stable heat sink connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional single-sided heat dissipation structure is used, then device simplicity is maintained, but heat dissipation efficiency is insufficient
Solution Approach 1:
The package structure is divided into upper and lower substrates with independent heat dissipation paths on each side. The chip is segmented to contact both upper and lower heat dissipation layers, creating parallel heat flow paths that improve overall heat dissipation efficiency without requiring a completely new package architecture.
Solution Approach 2:
The invention transitions from single-sided (2D) heat dissipation to double-sided (3D) heat dissipation by adding a lower heat dissipation path. Heat can now flow in multiple spatial directions simultaneously, effectively utilizing the third dimension (vertical depth) to enhance thermal management capability.
2Loss of energy
If metal frames and heat sink are tightly connected, then heat transfer is improved, but stress concentration and package cracking occur in high temperature or vibration environments
Solution Approach 1:
The thermal interface material is applied selectively at the contact interfaces between the chip and heat dissipation layers, and between substrates and heat sink. This localized application provides thermal compliance exactly where needed, allowing good thermal contact while accommodating differential thermal expansion without transmitting stress to the package structure.
Solution Approach 2:
A thermal interface material acts as an intermediary layer between rigid components (chip, substrates, heat sink). This mediator fills micro-gaps for thermal conduction while its compliant nature absorbs thermal expansion stresses, preventing stress concentration and package cracking during temperature cycling.
3Object-affected harmful factors
If traditional EMI shielding structure is used, then electromagnetic interference protection is limited, but structure complexity and cost increase
Solution Approach 1:
The upper and lower substrates serve dual functions: as mechanical support structures and as EMI shielding barriers. The metal traces and ground planes within the substrates create Faraday cage effects that block electromagnetic interference, eliminating the need for separate shielding components while providing both structural and electromagnetic protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances heat dissipation efficiency, reduces thermal stress, and improves EMI shielding, ensuring component stability and reliability in high-power applications.
Implementation Method 1
a lower substrate, which includes a lower ceramic substrate, a lower conductive layer and a lower heat dissipation layer, an upper substrate, which includes an upper ceramic substrate, an upper conductive layer and an upper heat dissipation layer
Implementation Method 2
bonding a metal tab to the lower substrate
Implementation Method 3
a molding material layer covering the chip and covering part of the lower substrate and the upper substrate
Data Source
AI summary
The invention provides a transistor outline (TO) packaging structure, which comprises a lower substrate, the lower substrate comprises a lower ceramic substrate, a lower conductive layer and a lower heat dissipation layer, an upper substrate, the upper substrate comprises an upper ceramic substrate, an upper conductive layer and an upper heat dissipation layer, a chip located between the lower substrate and the upper substrate, a molding material layer covering the chip and covering part of the lower substrate and the upper substrate, and a metal tab comprising an pin hole, wherein when from a cross-sectional view, a top surface of the upper substrate, a top surface of the metal tab, and a sidewall of the molding material layer form a stepped structure.