ToD-TC Module Phase Synchronization VDSL Clocks
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Solution Overview
Problem
Current VDSL systems fail to achieve phase synchronization for transporting time-of-day information, which is essential for accurately synchronizing network clocks across remote locations.
Innovation Solution
A method and system for synchronizing clocks at customer premises equipment (CPE) with a master clock at a central office (CO) using a time-of-day transmission convergence (ToD-TC) module, where time stamps are applied to reference data samples and transmitted to facilitate frequency and phase synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If loop timing configuration is used to frequency synchronize upstream transmit clock with downstream transmit clock, then frequency synchronization is achieved, but phase synchronization is not achieved which is essential for reporting time of day information
Solution Approach 1:
The patent introduces an intermediary mechanism (time stamping system and phase measurement protocol) to enable phase synchronization between CPE and CO clocks. The CPE timestamps downstream frames upon receipt and upstream frames upon transmission, then measures phase difference based on these timestamps. This intermediary measurement system resolves the contradiction by providing the missing phase synchronization capability while maintaining the existing frequency synchronization through loop timing.
2Measurement precision
If current VDSL system configuration is used, then system complexity is kept simple, but phase synchronization capability is missing which prevents accurate time-of-day information transport
Solution Approach 1:
The patent makes the existing loop timing configuration serve multiple functions: it continues to provide frequency synchronization while the newly added time stamping and phase measurement mechanisms provide phase synchronization. This multi-functionality approach enables accurate time-of-day information transport without requiring a completely separate synchronization system, thus limiting the increase in device complexity.
Solution Approach 2:
The patent changes the operational parameters of the existing VDSL system by adding time stamping capabilities and phase measurement procedures. Instead of fundamentally redesigning the synchronization architecture, it modifies the temporal parameters (adding timestamp fields, measuring phase differences) to enable phase synchronization while keeping the core loop timing structure intact.
3Reliability
If phase synchronization is implemented to enable accurate time-of-day information transport, then time synchronization accuracy is improved, but system complexity increases due to additional synchronization mechanisms
Solution Approach 1:
The patent implements preliminary time stamping of downstream and upstream frames at the CPE before phase measurement is performed. By pre-stamping the frames with timestamps when they are received and transmitted, the system prepares the necessary data in advance for phase calculation. This preliminary action simplifies the overall process by avoiding complex real-time measurements and reduces the computational complexity of the phase synchronization mechanism.
Data Source
AI summary
Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that comprises receiving, by a time-of-day transmission convergence (ToD-TC) module in the CPE, ToD information relating to the master clock. Based on the received information, time stamps are applied to reference data samples. The method further comprises transporting the ToD information by transporting the reference data samples with applied time stamps and utilizing time stamps of the reference data samples to synchronize the CPE clock with the master clock.