TOE Memory Hierarchy for High-Connection TCP Offload

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Solution Overview

Problem

Network devices require efficient and flexible hardware/software design to handle high-speed network environments and large data processing loads, particularly in devices like web servers, where CPU load from TCP/IP operations leads to performance degradation and communication delays.

Innovation Solution

A TOE-based network interface device with a memory hierarchy structure that distributes TCP connection information across small but fast memory (SRAM) and slow but large capacity memory (DRAM), using a scheduler and memory manager to optimize TCP operations and prevent performance degradation during memory swapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If TCP connection information is stored only in fast memory (SRAM) to improve processing speed, then TCP operation performance is improved, but the number of supported TCP connections is limited due to small memory capacity

Engineering Contradiction:
ImproveTCP operation speedVSAvoidnumber of TCP connections
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent divides the memory storage system into two segments: fast memory (SRAM) and slow memory (DRAM). TCP connection information is segmented and stored in appropriate memory types based on access frequency and performance requirements. This segmentation allows the system to support a large number of TCP connections while maintaining high performance for active connections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to memory management by implementing a hierarchical memory structure with multiple levels (SRAM and DRAM). This dimensional change from a single memory space to a multi-level memory hierarchy enables the system to overcome the capacity limitations of fast memory while preserving its speed advantages for critical operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If TCP connection information is distributed across fast and slow memory to increase capacity, then the number of supported TCP connections increases, but performance degradation occurs during memory swapping

Engineering Contradiction:
Improvenumber of TCP connectionsVSAvoidprocessing efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent implements preliminary actions by pre-loading frequently accessed TCP connection information into fast memory (SRAM) before it is needed for processing. The system proactively manages memory swapping operations to ensure that hot data is already in the fast memory when required, thereby avoiding performance degradation during actual TCP operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism (memory management unit/controller) that mediates between the fast and slow memory. This intermediary intelligently manages data transfer and swapping operations, optimizing the interaction between SRAM and DRAM to minimize performance impact while maximizing the number of supported TCP connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If CPU performs TCP/IP operations directly to simplify system architecture, then device complexity is reduced, but CPU load increases leading to performance degradation

Engineering Contradiction:
Improvesystem architecture complexityVSAvoidoverall system performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent extracts the TCP/IP processing functions from the main CPU and implements them in a separate network interface device with dedicated hardware. This extraction removes the burden of TCP/IP operations from the CPU, allowing the CPU to focus on higher-level application logic while the network device handles protocol processing independently, thereby improving overall system performance without significantly increasing complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12519728B2Toe-based network interface device including memory hierarchy structure and operation method thereof
Publication Date: 2026.01.06 MANGOBOOST INC
  • US12519728B2 patent drawing
  • US12519728B2 patent drawing
  • US12519728B2 patent drawing

AI summary

A network interface device and an operation method thereof are disclosed. A network interface device for this purpose may include: a scheduler configured to schedule a TCP event, and to forward the TCP event to the location based on a location reference table indicating a location of TCP connection information corresponding to the TCP event; at least one TCP controller configured to obtain the TCP event from the scheduler, and to control operations for the TCP connection information corresponding to the TCP event; and a memory manager configured to obtain the TCP event from the scheduler, to determine whether to perform TCP operations for the TCP connection information corresponding to the TCP event, and to transmit a swapping request signal to the scheduler requesting to move the TCP connection information to a TCP controller among the at least one of the TCP controllers based on the result of the determination.