TOE Network Interface Device Offloading TCP/IP Load
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Solution Overview
Problem
In high-speed network environments, the significant load on host CPU CPUs during TCP/IP operations in web servers leads to performance deterioration and delayed network communication due to the high resource requirements for data throughput and processing.
Innovation Solution
A TOE-based network interface device with an event scheduler, multiple TCP controllers, and memory control logic that offloads TCP/IP operations from the host CPU by storing connection information in a first memory and moving it to a second memory when events do not occur, optimizing data processing and reducing CPU load through parallel processing and optimized scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TCP/IP operations are performed by host CPU in high-speed network environment, then data communication functionality is achieved, but host CPU load increases significantly causing performance deterioration
Solution Approach 1:
The patent extracts TCP/IP processing functionality from the host CPU and relocates it to a dedicated network interface device. The network interface device includes event scheduler, TCP controllers, and arithmetic logic units that independently handle TCP/IP operations, thereby relieving the host CPU from significant computational load while maintaining full data communication functionality.
Solution Approach 2:
The network interface device acts as an intermediary between the network and the host CPU. It includes reception and transmission processing modules that handle data packet processing, parsing, and protocol operations, serving as a mediator that prevents direct CPU involvement in resource-intensive TCP/IP arithmetic operations.
2Speed
If connection information is stored in first memory of TCP controller, then event processing speed is improved, but memory usage increases when events do not occur frequently
Solution Approach 1:
The patent implements a dynamic memory management system where connection information is stored in the first memory (fast memory) of TCP controllers when events are active, and automatically moved to the second memory (main memory) when events become inactive. The event scheduler monitors event status and dynamically relocates connection information based on activity levels, optimizing both speed and memory utilization.
Solution Approach 2:
The system performs preliminary actions by pre-allocating memory structures in both first and second memories, and establishing automatic migration triggers based on event timing. When events do not occur for specified time periods, the connection information is proactively moved to second memory before memory resources are critically needed, preventing performance degradation.
3Productivity
If multiple TCP controllers are provided for parallel processing, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the network interface device into multiple independent TCP controllers (first TCP controller, second TCP controller, etc.), each capable of handling specific connection events independently. Each controller has its own arithmetic logic unit and first memory, enabling parallel processing of multiple data streams simultaneously while maintaining modular architecture that manages complexity through functional decomposition.
Data Source
AI summary
A TOE-based network interface device, a method of operating the same, and a server device including the same are provided. The network interface device includes an event scheduler configured to generate connection information on a requested event and to perform scheduling on the connection information to output a first control signal, a first TCP controller and a second TCP controller, each configured to receive the connection information from the event scheduler and to control an arithmetic operation on the connection information, and a memory control logic configured to transmit the connection information to a first memory or to store the connection information in a second memory in response to the first control signal.