Substrate-Biased ToF Image Sensor for Low-Noise Depth Sensing
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Solution Overview
Problem
Existing indirect time-of-flight image sensors face challenges in efficiently determining depth maps due to high power consumption and noise issues associated with controlling transfer gates at high frequencies.
Innovation Solution
The image sensor design includes an array of pixels with a semiconductor substrate, where each pixel has a photoconversion area and memory areas coupled by transfer gates, with a bias voltage applied to the substrate to block or enable charge transfer, using a switched-mode power supply and low dropout regulators to manage power and noise, and capacitive elements to optimize operation during integration and readout phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transfer gates are controlled at high frequencies to enable fast charge transfer between memory areas, then the speed of depth map determination is improved, but power consumption increases and noise is generated
Solution Approach 1:
The patent applies periodic action by controlling transfer gates to operate only during specific integration phases rather than continuously. The circuit applies bias voltage to the substrate during integration phases when charge transfer is needed, and removes it during readout phases, creating a periodic operation pattern that reduces overall power consumption while maintaining high-speed charge transfer capability when required.
Solution Approach 2:
The patent changes the electrical parameter (substrate bias voltage) dynamically based on operational phase. During integration phases, a first bias voltage is applied to enable high-frequency charge transfer; during readout phases, a second bias voltage is applied to block charge transfer and reduce power consumption. This parameter change allows the system to achieve high speed when needed while minimizing energy consumption during other phases.
2Productivity
If transfer gates are controlled at high frequencies to enable fast charge transfer, then productivity is improved, but noise is generated that degrades measurement precision
Solution Approach 1:
The circuit enables high-frequency transfer gate operation periodically during integration phases to maintain productivity, while during readout phases it applies different bias conditions that block charge transfer and eliminate the associated noise. This periodic modulation allows the system to achieve high efficiency during data accumulation while ensuring measurement precision during data readout.
Solution Approach 2:
The patent rushes through the charge transfer operation during integration phases by applying appropriate bias voltages that enable fast transfer, then quickly transitions to the readout phase where charge transfer is blocked. This skipping of unnecessary charge transfer during readout prevents noise generation while maintaining overall productivity through efficient phase transitions.
3Use of energy by moving object
If bias voltage is applied to substrate to block transfer gates during readout phase, then power consumption is reduced, but device complexity increases due to additional voltage control circuits
Solution Approach 1:
The circuit is designed to perform multiple functions: it controls the substrate bias voltage to enable charge transfer during integration phases, blocks charge transfer during readout phases, and manages power distribution to transfer gates. By making this single circuit multi-functional, the patent reduces overall device complexity despite the additional control capabilities required for power management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption and noise, enhancing the accuracy and efficiency of depth map determination while maintaining high frequency operation, thus improving the image sensor's performance and reducing bulkiness and cost.
Implementation Method 1
a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it
Implementation Method 2
in each pixel, charges are then photogenerated in a photoconversion area of the pixel
Implementation Method 3
each pixel comprises at least one detection node connected to an electrode of a capacitive element, preferably of metal-insulator-metal type, the other electrode of the capacitive element being connected to ground
Data Source
AI summary
The present description describes an image sensor including an array of pixels arranged inside and on top of a region of a semiconductor substrate electrically insulated from the rest of the substrate by insulating trenches crossing the substrate, each pixel including a photoconversion area and at least two assemblies, each including a memory area and a transfer gate coupling the memory area to the photoconversion area, and a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it.