ToF Imaging Element Dual-Surface Wiring for Fast Charge Transfer
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Solution Overview
Problem
In indirect Time of Flight (ToF) distance measurement schemes, there is a need for high-speed charge distribution and transfer between electrodes, requiring low resistance and low capacity wiring connected to the gate of a transfer transistor, especially for large pixel arrays like 1 M pixels where driving is performed at several hundreds of MHz.
Innovation Solution
The implementation of a semiconductor substrate with a matrix arrangement of pixels including photodiodes, first and second transfer transistors, and a laminated wiring layer where the first and second transfer transistors are connected on opposite surfaces, allowing for efficient charge transfer and distribution across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wiring connected to transfer transistor gates is made conventional, then device complexity is reduced, but resistance and capacity increase causing slow charge transfer
Solution Approach 1:
The patent applies dimensionality change by routing wirings on both the front surface and back surface of the wiring layer. Specifically, first wirings are provided on the front surface side while second wirings are provided on the back surface side, creating a three-dimensional wiring architecture that reduces resistance and capacity without increasing planar complexity. This allows charge to be transferred more efficiently from photodiodes through transfer transistors to charge storage regions.
2Productivity
If wiring resistance and capacity are reduced for high-speed operation, then charge transfer speed improves, but wiring layer structure becomes more complex
Solution Approach 1:
The patent segments the wiring function across multiple layers and surfaces. The wiring layer is divided into first wirings on the front surface and second wirings on the back surface, with each segment serving specific functions. This segmentation allows optimization of each wiring segment for low resistance and low capacity while maintaining overall structural organization, enabling high-speed charge distribution in 1M-pixel arrays operating at several hundreds of MHz.
3Reliability
If conventional wiring layout is used, then manufacturing is simpler, but charge transfer efficiency decreases at high pixel counts
Solution Approach 1:
The patent utilizes the third dimension (depth/thickness) of the wiring layer by providing wirings on both front and back surfaces. This vertical dimensionality change enables shorter current paths and reduced parasitic effects, improving charge transfer reliability for high-resolution imaging. The dual-surface wiring approach can be integrated into existing CMOS manufacturing processes through standard thin-film deposition and patterning techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables low resistance and low capacity connections, facilitating high-speed charge transfer and accurate distance measurement in ToF schemes, particularly for high-resolution pixel arrays, enhancing the efficiency and precision of distance measurement systems.
Implementation Method 1
a distance is indirectly measured by performing photoelectric conversion in a sensor
Data Source
AI summary
The present technique relates to an imaging element, an imaging device, and electronic equipment that enable a wiring capacity and a resistance to be reduced. A semiconductor layer in which pixels including photodiodes, first transfer transistors, and second transfer transistors are arranged in a matrix shape and a wiring layer on the semiconductor layer are included, and a first wiring to which the first transfer transistors of the plurality of pixels arranged in a row direction or a column direction from among the pixels are connected and a second wiring to which the second transfer transistors of the plurality of pixels are connected are included on a side of a second surface of the wiring layer that is opposite to a first surface on which the semiconductor layer is laminated. The present technique can be applied to an imaging element that performs distance measurement, for example.