Time of Flight Measurement Circuit Using Multi-Phase Clock Delay Latching
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Solution Overview
Problem
Existing Time to Digital Convert (TDC) chip circuits face challenges in achieving high-resolution time measurements due to cost and environmental limitations, limiting their ability to meet high-resolution measurement requirements.
Innovation Solution
A time of flight measurement method and circuit that involves performing delay processing on an echo signal to generate multiple delayed signals, using a multi-phase clock unit to generate clock signals with different phases, and performing delay latching to determine the target time of flight, thereby improving precision while reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TDC chip circuit is implemented using a gate circuit and carry chain of FPGA to achieve high time resolution, then measurement precision is improved, but cost and device complexity increase
Solution Approach 1:
The patent segments the time measurement function into multiple parallel measurement paths, each handling a specific time range. The TDC chip divides the total measurement range into several segments, with each segment processed by dedicated delay units and counters. This segmentation allows high precision measurement without requiring a single complex circuit to handle the entire range, thus reducing overall device complexity while maintaining measurement precision.
2Measurement precision
If the minimum delay of the carry chain of FPGA is used to determine time difference precision, then measurement precision is improved, but cost increases due to requirements for high-performance components
Solution Approach 1:
The patent changes the measurement parameters by using multiple measurement paths with different delay characteristics. Instead of relying solely on the minimum delay of a single carry chain, the system uses multiple delay units with varying delay values (first delay value, second delay value, etc.) and combines their measurements. This parameter diversification allows achieving high precision time difference measurement using standard FPGA components rather than requiring expensive high-performance carry chains with precisely controlled minimum delays.
3Measurement precision
If multiple delay units with different delay values are used to perform delay processing on echo signal, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple measurement results from different delay units through a unified processing architecture. Multiple delay units with different delay values process the echo signal in parallel, and their respective time of flight measurements are combined using a weighted average or selection algorithm. This merging approach allows the system to achieve high precision equivalent to having a single complex delay unit while using multiple simpler, standardized delay units that can be implemented using regular FPGA logic resources.
Data Source
AI summary
The embodiments of this application disclose a time of flight measurement method, including: performing delay processing on an echo signal to obtain N delayed signals; generating X clock signals with different phases based on a multi-phase clock unit; performing delay latch on the N delayed signals based on each of the X clock signals; determining a to-be-processed time of flight based on the reference signal and each of the delay latch result; and determining a target time of flight based on the X to-be-processed time of flights, where the target time of flight is a time difference between emitting the reference signal and receiving the echo signal. With the embodiment of this application, the precision of measuring the time of flight of the echo signal can be effectively improved while saving costs and simplifying calculations.