ToF Image Sensor Phase-Delay Clocking for Noise Reduction

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Solution Overview

Problem

Time-of-flight (ToF)-based image sensors suffer from measurement noise that decreases the accuracy of distance information due to various causes.

Innovation Solution

An image sensor that includes a phase select circuit with a plurality of delay circuit cells, generating delay clock signals of different phases for each pixel group during different integration times to reduce noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single clock signal is used for all pixels, then the device complexity is low, but measurement noise increases and measurement precision deteriorates

Engineering Contradiction:
Improvedistance measurement accuracyVSAvoidclock signal generation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The pixel array is divided into multiple pixel groups, and each pixel group is assigned a unique delay clock signal with a different phase. This segmentation allows each group to perform distance measurements at different time points, reducing noise through temporal diversity while maintaining manageable system complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs periodic delay clock signals with different phases for different pixel groups. By periodically varying the clock phases and integrating signals over multiple periods, the system achieves noise reduction through temporal averaging while maintaining a regular, predictable signal structure that simplifies control.

Inventive Principle:
Principle #19Periodic action

2Measurement precision

If multiple delay clock signals with different phases are generated for different pixel groups, then measurement noise is reduced and measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvedistance measurement accuracyVSAvoidphase select circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

A phase select circuit is introduced as an intermediary component that receives a single reference clock signal and generates multiple delay clock signals with different phases. This intermediary structure simplifies the overall system by centralizing the complex signal generation function in a dedicated circuit, rather than requiring complex control logic throughout the pixel array.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the phase parameter of the clock signal for different pixel groups. By varying only the phase parameter while maintaining the same frequency and amplitude, the system achieves noise reduction without requiring fundamentally different signal generation mechanisms for each pixel group, thus controlling complexity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If delay clock signals are generated for each pixel group, then the quantity of useful action increases through parallel noise reduction, but loss of time occurs due to additional signal processing

Engineering Contradiction:
Improvenoise reduction efficiencyVSAvoidsignal processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The phase select circuit generates all required delay clock signals with different phases in advance, before the actual distance measurement begins. This preliminary preparation of clock signals allows the pixel groups to immediately start their parallel measurements without waiting for sequential clock generation, thus reducing overall processing time while maintaining noise reduction effectiveness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system combines the clock signal generation function for all pixel groups into a single phase select circuit. By merging the generation of multiple delay clock signals into one centralized circuit, the system achieves parallel signal distribution to all pixel groups simultaneously, maximizing productivity while minimizing the time lost to sequential processing.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively reduces measurement noise, enhancing the accuracy of distance information obtained by the image sensor.

Implementation Method 1

The phase select circuit outputs delay clock signals of different phases from each other to an object pixel in response to different integration times from each other in a frame

Methodology Applied
Scientific EffectPhase delay:

Implementation Method 2

ToF-based image sensors obtain information about the distance to the object by irradiating the object with a light beam, and measuring the ToF of the light beam until the light beam reflected by the object is received

Methodology Applied
Scientific EffectTime of flight: Time of Flight

Implementation Method 3

Each pixel outputs a pixel signal corresponding to a photoelectric signal in response to a photo gate signal

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS12571917B2Image sensor operating based on plurality of delay clock signals
Publication Date: 2026.03.10 SAMSUNG ELECTRONICS CO LTD
  • US12571917B2 patent drawing
  • US12571917B2 patent drawing
  • US12571917B2 patent drawing

AI summary

An image sensor includes a plurality of pixels and a phase select circuit. Each pixel outputs a pixel signal corresponding to a photoelectric signal in response to a photo gate signal. The phase select circuit outputs delay clock signals of different phases from each other to an object pixel in response to different integration times from each other in a frame. The phase select circuit includes a plurality of delay circuit cells corresponding to at least some pixels of the plurality of pixels. Each of the plurality of delay circuit cells generates a delay clock signal of a certain phase difference from any one of a reference clock signal and an output signal of another delay circuit cell according to a logic state of a select signal.