Toggle-Signal Clock Synchronization for Mixed-Frequency Circuits
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Solution Overview
Problem
Existing clock signal frequency dividing circuits fail to efficiently communicate between circuits operating at different frequencies, leading to increased power consumption, circuit scale, and design costs due to the need for special clock switching or timing designs.
Innovation Solution
A processing device and method that uses a toggle signal and marker parts to synchronize communication between circuits with different clock frequencies, employing a clock signal frequency dividing circuit that generates a frequency-divided clock signal with masked pulses and marker patterns to facilitate efficient inter-block data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a frequency dividing circuit masks M-N clock pulses among M consecutive clock pulses to generate a frequency-divided clock signal at ratio N/M, then the target circuit can operate at a lower frequency, but communication timing becomes complex and design cost increases
Solution Approach 1:
The frequency division ratio is predetermined and stored in advance in a register. The mask control circuit uses this pre-stored ratio to generate mask signals without requiring real-time calculation or complex timing design, thereby simplifying the communication timing while enabling frequency division for reduced power consumption
Solution Approach 2:
A mask control circuit is introduced as an intermediary component that receives the input clock signal and frequency division ratio, then generates appropriate mask signals to control the mask circuit. This intermediary simplifies the overall system by centralizing the frequency division control logic, reducing design complexity while enabling power-efficient operation at divided frequencies
2Adaptability or versatility
If special clock switching or timing designs are used to communicate between circuits with different frequencies, then communication between circuits is enabled, but circuit scale and design costs increase
Solution Approach 1:
The frequency dividing circuit is designed to be universally applicable to any target circuit requiring a lower operating frequency. By using a programmable frequency division ratio stored in a register, the same circuit structure can adapt to different frequency requirements without requiring specialized clock switching designs, thereby enabling versatile communication while maintaining compact circuit scale
Solution Approach 2:
The frequency division ratio is implemented as a changeable parameter stored in a register rather than a fixed hardware configuration. This allows the circuit to adapt to different frequency requirements by simply changing the stored ratio value, enabling versatile communication between circuits with different frequencies without increasing circuit scale or requiring complex timing designs
3Productivity
If a frequency dividing circuit with ratio N/M is used to generate lower frequency clock signals, then optimum operating frequency for each circuit block is achieved, but the circuit becomes more complex compared to integer division
Solution Approach 1:
The frequency division ratio N/M is predetermined and stored in a register before operation. This preliminary setup allows the mask control circuit to generate mask signals based on pre-calculated timing information, achieving the optimum operating frequency for signal processing efficiency while avoiding the complexity of real-time ratio calculation or conversion circuits
Solution Approach 2:
The patent replaces complex mechanical or hardware-based frequency division mechanisms with a software-like approach using registers to store frequency division ratios and mask control circuits to generate timing signals. This substitution achieves rational number frequency division (N/M) with simpler circuitry compared to traditional integer-only division circuits, enabling optimized signal processing without excessive complexity
Data Source
AI summary
A processing device according to an aspect of the present disclosure includes: a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.