Toggle-Based FIFO Buffer for Clock Domain Crossing
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Solution Overview
Problem
As data processing speeds increase, existing clock domain crossing elements face challenges in efficiently transferring data between synchronous circuits operating at different clock frequencies, leading to issues like overflows, underflows, and desynchronization.
Innovation Solution
The implementation of a high-performance dual clock FIFO buffer with a toggle-based pointer management circuitry that uses toggle encoding and feedback-based handshakes to manage buffer pointers across clock domains, ensuring robust data transfer and preventing glitches, while also enabling improved pre-fetch read instructions and robust reset procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock speeds in synchronous circuitry are increased to meet faster data processing demands, then data processing speed is improved, but the reliability of data transfer between clock domains deteriorates due to overflows, underflows, and desynchronization
Solution Approach 1:
The patent implements feedback-based handshake protocols where the transmitting and receiving clock domains exchange status information (empty/full flags, read/write pointers) through synchronized feedback paths. This feedback mechanism allows each domain to monitor the other's state and adjust timing accordingly, preventing overflows and underflows even at high clock speeds, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent employs preliminary actions by pre-loading data into the FIFO buffer before actual consumption and by establishing synchronized handshake signals before data transfer begins. The toggle-based pointer management circuitry performs preliminary synchronization of read and write pointers across clock domains, ensuring that data is ready and timing is aligned before high-speed transfer commences, thereby maintaining reliability at increased speeds.
2Device complexity
If existing clock domain crossing elements are used for data transfer, then device complexity is reduced, but data transfer efficiency and latency performance deteriorate
Solution Approach 1:
The patent segments the clock domain crossing element into distinct functional modules: a FIFO buffer for data storage, toggle-based pointer management circuitry for synchronization, and feedback handshake protocols for coordination. This segmentation allows each module to be optimized independently for high-speed operation while maintaining overall manageability, improving data transfer efficiency without excessive complexity.
Solution Approach 2:
The patent utilizes parameter changes through toggle-based encoding of pointer values and dynamic adjustment of handshake signal timing based on clock domain frequency differences. By changing the encoding parameters and timing parameters adaptively, the system achieves high data transfer efficiency and low latency while keeping the circuit implementation relatively simple, resolving the contradiction between complexity and productivity.
3Ease of operation
If conventional pointer management is used across clock domains, then ease of operation is maintained, but data transfer latency increases and efficiency decreases
Solution Approach 1:
The patent replaces conventional mechanical-style sequential pointer incrementation with a parallel toggle-based encoding system that simultaneously updates read and write pointers across clock domains. This substitution allows pointer management to occur in parallel with data transfer operations, dramatically reducing latency while maintaining ease of operation through automated synchronized updates, thus resolving the contradiction between operational simplicity and time loss.
Data Source
AI summary
The disclosure relates to clock-crossing elements that may be used to transfer data between different clock domains. The embodiments include dual clock first-in first-out (FIFO) buffers that may employ toggle-based protocols to manage the transference of information regarding the state of the FIFO buffer. The toggle-based protocols may include a feedback-based handshake and bit-sliced toggle lines to prevent errors due to differences between the clock signals in the different clock domains.