Toggle MRAM Burst Writes Using Parallel Read Comparison
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Solution Overview
Problem
Toggle memories, such as certain types of magnetoresistive random access memory (MRAM) cells, require a read operation to determine the current state before writing, making the write cycle slower due to the need to differentiate resistance values.
Innovation Solution
A toggle memory system with control circuitry that enables burst writes by reading multiple cells in parallel and generating toggle instructions based on comparison of read and write data, allowing for simultaneous toggling of cells without requiring a read for each write operation, thereby reducing the time needed for a write cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read operation is performed before each write cycle to determine the current state of the cell, then data integrity is maintained, but the writing process becomes slower
Solution Approach 1:
The patent performs read operations in advance for multiple cells (e.g., 4 cells) and stores the read data in buffer registers before the actual write operations begin. This preliminary reading eliminates the need to read each cell individually before every write cycle, thereby maintaining data integrity while significantly improving write speed.
Solution Approach 2:
The patent divides the write operation into segments where data for multiple cells is prepared and buffered separately. By segmenting the read and write operations into distinct phases (read phase followed by write phase), the system can process multiple cells more efficiently without compromising the required read-before-write protocol for each cell.
2Measurement precision
If individual read cycles are performed for each cell before writing, then accurate state determination is achieved, but the write burst time increases
Solution Approach 1:
The patent performs read operations in advance for multiple cells (e.g., 4 cells) and stores the read data in buffer registers before the actual write operations begin. This preliminary reading eliminates the need to read each cell individually before every write cycle, thereby maintaining data integrity while significantly improving write speed.
Solution Approach 2:
The patent merges the read operations for multiple cells into a single parallel read phase, followed by a merged write phase. By combining the read operations for multiple cells into one batch operation rather than sequential operations, the system reduces the total time required while maintaining accurate state determination for each cell.
3Productivity
If parallel reading of multiple cells is implemented, then write throughput is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple banks or groups of cells that can be read and written in parallel. By segmenting the memory structure and associated control circuitry, the system achieves parallel processing capability while keeping each segment's complexity manageable. The control circuitry is divided into separate units that can independently handle read and write operations for different cell groups.
Solution Approach 2:
The patent designs the control circuitry to perform multiple functions: it can read multiple cells in parallel, buffer the read data, compare the read data with desired write data, and generate appropriate write signals. This multi-functional approach reduces the need for separate dedicated circuits for each function, thereby improving write throughput while limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for a write burst by performing a single read cycle for multiple cells, significantly improving the write efficiency compared to traditional methods that would require a read before each toggle operation.
Implementation Method 1
memory cells each having multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions
Implementation Method 2
the state of the cell is differentiated by the resistance of the magnetic tunnel junction of the cell
Data Source
AI summary
A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.