Toggle Pattern Phase Alignment for High-Speed Signal Generation

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Solution Overview

Problem

Existing signal generation systems struggle to adjust phase differences between signals input to a multiplexer (MUX) beyond 1 UI, leading to data errors and the need for additional mechanisms and frequent recalibration, especially in high-speed applications like 32 Gsps with 8-bit resolution.

Innovation Solution

A signal generation apparatus and method that includes a phase synchronization control unit to adjust phase differences between transceivers, using a division clock, phase demodulation, and clock selection to reduce maximum phase differences to 0.1 UI or less, without requiring external delay circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the phase difference adjustment range is extended beyond 1 UI, then the signal generation accuracy deteriorates due to data errors, but the system complexity increases requiring additional mechanisms and frequent recalibration

Engineering Contradiction:
Improvephase difference adjustment accuracyVSAvoidsystem complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces a delay line as an intermediary component between the transceiver outputs and the multiplexer input. This delay line acts as a dedicated phase adjustment mechanism that can precisely control signal phase without requiring complex external circuits or frequent recalibration, thereby resolving the contradiction between adjustment accuracy and system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter of phase adjustment by implementing a delay line with adjustable delay amounts corresponding to different UI (unit interval) values. This allows the system to achieve phase differences beyond 1 UI by selecting appropriate delay amounts, maintaining signal accuracy while avoiding the need for additional complex mechanisms

Inventive Principle:
Principle #35Parameter changes

2Speed

If the output rate is increased to 32 Gsps with 8-bit resolution, then the signal transmission speed improves, but the phase difference control precision deteriorates requiring maximum phase difference less than 0.1 UI

Engineering Contradiction:
Improveoutput rateVSAvoidphase difference control precision
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent segments the phase adjustment function into discrete delay amounts (e.g., 0.5 UI, 1.0 UI, 1.5 UI, 2.0 UI) that can be selectively applied to different transceiver outputs. This segmentation allows precise phase control at high speeds by selecting appropriate delay segments, achieving the required 0.1 UI precision without compromising the 32 Gsps output rate

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies delay adjustment in advance before the signals are multiplexed and output. By pre-adjusting the phase of each transceiver output using the delay line, the system ensures that signals are properly synchronized before entering the multiplexer, maintaining precision at high speeds without requiring post-processing or frequent recalibration

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12438756B2Signal generation apparatus and signal generation method
Publication Date: 2025.10.07 ANRITSU CORP
  • US12438756B2 patent drawing
  • US12438756B2 patent drawing
  • US12438756B2 patent drawing

AI summary

The signal generation apparatus includes a phase difference calculation processing unit that calculates an initial phase difference between a division clock or an external clock selected by a clock selection unit and an initial value of the phase of the toggle pattern based on a relationship between the voltage value acquired by the phase acquisition processing unit and a change amount from the initial value of the phase of the toggle pattern, and a phase shift processing unit that moves the phase of the toggle pattern from the initial value by the initial phase difference such that a phase difference between the division clock or the external clock selected by the clock selection unit and the toggle pattern is within a predetermined range.