Toggleable Memory Tagging Extension for Processor Performance
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Solution Overview
Problem
Current computing systems face challenges in balancing memory security and performance, as mechanisms like memory tagging extensions (MTE) can improve security but come at the cost of reduced performance due to the need for read operations before writes, which can slow down processing.
Innovation Solution
The introduction of toggleable memory tagging extensions in processing circuits allows for two modes of operation: one prioritizing security by enabling memory tagging and another prioritizing performance by disabling it, thereby eliminating the need for a read before a write operation, which improves processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory tagging extension is enabled to improve memory security, then unauthorized access detection capability is improved, but processing performance deteriorates due to additional read operations required before write operations
Solution Approach 1:
The patent implements a dynamic memory tagging extension that can be selectively enabled or disabled based on operational requirements. The system transitions from a static security mechanism to a dynamic one that adapts its behavior, allowing the processor to switch between security-focused mode (with tag checking) and performance-focused mode (without tag checking), thereby resolving the contradiction between security and performance
Solution Approach 2:
The patent changes the operational parameter of the memory tagging extension from a fixed state to a variable state. By modifying the enable/disable parameter of the MTE based on different operational contexts, the system can optimize for either security or performance as needed, directly addressing the technical contradiction between these two opposing requirements
2Reliability
If memory tagging extension performs read operation before write operation to verify authorization, then memory access control is improved, but processing speed deteriorates
Solution Approach 1:
The patent makes the tag verification process dynamic by allowing the system to switch between performing read-before-write operations (when security is prioritized) and direct write operations (when speed is prioritized). This dynamic adjustment of the verification process resolves the contradiction between access control reliability and processing speed
Solution Approach 2:
The patent extracts the tag verification step from the mandatory write path, allowing it to be selectively applied. When performance is prioritized, the verification step is removed from the critical path, enabling direct writes without the overhead of prior read operations, thus resolving the speed-control contradiction
Data Source
AI summary
In processors that include a memory tagging extension (MTE), before reading data from or writing data into a memory address, tag bits associated with the memory address are read from the memory and compared to tag bits in the instruction target address. This delays memory write instructions that would not otherwise have to perform a read from the memory circuit before executing the write operation (e.g., full cache line writes), reducing processor performance. An exemplary processing circuit includes a toggleable MTE to provide access to a memory circuit in one of a first mode, in which a memory tagging extension is enabled, and a second mode, in which the MTE is disabled. The processing circuit includes an execution circuit to process a memory instruction and a load/store circuit that does not read the tag bits when MTE is disabled, thereby reducing execution time of the memory instruction.