Token-Based Error Detection for Reconfigurable Hardware Address Channels
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Solution Overview
Problem
Current intra-chip communication protocols, such as AMBA AXI, lack error detection mechanisms, making them insecure and unreliable for multi-tenant reconfigurable hardware systems, where fault injection attacks can occur due to shared power sources and aggressive resource utilization, potentially leading to unauthorized access and data corruption.
Innovation Solution
Implementing error detection methods through token-based verification for address channels and check bit-based verification for data channels, using XOR operations and complementary check bits to identify and correct errors, thereby enhancing the security and reliability of intra-chip communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection mechanisms are implemented in intra-chip communication protocols, then security and reliability are improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by generating and applying tokens to requests before transmission over the address channel, and generating check bits for data before transmission. This proactive error detection approach allows the system to identify communication errors before they can cause security breaches or data corruption, thereby improving reliability without requiring complex post-transmission verification mechanisms
Solution Approach 2:
The patent introduces tokens and check bits as intermediary elements that facilitate error detection. These intermediaries are applied to requests and data respectively, enabling the detection of fault injection attacks and transmission errors without requiring direct complex verification of the underlying communication protocol, thus resolving the contradiction between reliability improvement and protocol complexity
2Object-affected harmful factors
If token-based verification is applied to address channels, then fault injection attack detection is improved, but processing time increases
Solution Approach 1:
The patent employs parameter changes by utilizing simple XOR operations between tokens and requests, and between check bits and data. These bitwise operations can be executed extremely quickly in hardware, providing robust fault injection attack detection while minimizing the time added to request processing. The use of predetermined tokens and systematic check bit generation further optimizes the processing time
3Reliability
If check bit-based verification is applied to data channels, then data transmission reliability is improved, but processing overhead increases
Solution Approach 1:
The patent applies partial action by generating check bits for data transmission without requiring full re-transmission or complex verification protocols. The check bits provide sufficient error detection capability for data channels while avoiding the excessive processing overhead that would result from more comprehensive verification mechanisms, thus improving reliability with minimal processing burden
Data Source
AI summary
Systems and methods for error detection for an address channel are disclosed. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request with the first result is transmitted to a destination over the address channel. A determination is made, at the destination, whether an error associated with the request has occurred. The determining whether the error has occurred includes: receiving a received request corresponding to the request over the address channel; receiving the first result with the received request; applying the token to the received request and generating a second result; comparing the first result with the second result; and transmitting a signal in response to the comparing.