Reconfigurable Processor Token Network Reduces Configuration Memory Power
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Solution Overview
Problem
In reconfigurable processors with a large number of processing elements, the high frequency of configuration memory access leads to increased power consumption due to the need for frequent reading and supplying of instructions, which is inefficient and power-intensive.
Innovation Solution
A processor with a reconfigurable architecture that includes a token network to estimate and manage data flow between processing elements, reducing the need for frequent configuration memory access by processing and supplying only the necessary configuration data, and using a single physically implemented control memory across nodes to minimize memory access frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of PEs exist or if a word is particularly long, then the processing capability is improved, but the configuration memory access frequency increases which results in increased power consumption
Solution Approach 1:
The patent segments the configuration data into multiple parts or fields within the instruction structure. Each instruction contains multiple fields that can be selectively accessed and supplied to different PEs, allowing the system to handle large numbers of PEs without requiring a single large memory access, thereby reducing overall memory access frequency and power consumption.
Solution Approach 2:
The patent implements partial action by selectively supplying only the needed configuration data parts to the appropriate PEs based on the current processing requirements. The instruction structure allows the memory controller to access and transmit only necessary fields rather than entire configuration words, reducing memory access frequency while maintaining processing capability for large PE arrays.
2Ease of operation
If configuration memory access frequency increases to supply instructions to all PEs, then the data flow control is improved, but the power consumption of the processor increases
Solution Approach 1:
The patent implements preliminary action by pre-organizing configuration data into structured instructions that contain multiple fields ready for selective access. The memory controller is designed to efficiently extract and supply only the necessary fields to PEs based on current data flow requirements, avoiding unnecessary memory accesses and reducing power consumption while maintaining effective data flow control.
Solution Approach 2:
The patent changes the parameter of memory access by transitioning from frequent full-word accesses to selective field accesses within instructions. The structured instruction format allows the system to vary the amount and type of data accessed based on processing needs, reducing memory access frequency and associated power consumption while maintaining adequate data flow control for all PEs.
Data Source
AI summary
Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.