Token Ring Loops in Stack Packages
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Solution Overview
Problem
Stack packages face increased power consumption due to maximum current flow through semiconductor chips when using traditional bonding wire connections, which are not efficiently managed.
Innovation Solution
Implementing token ring loops that electrically connect semiconductor chips through a series of interconnections between bond fingers and bonding pads, reducing current flow by serially connecting the chips and utilizing dummy pads to manage signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bonding wire connections are used to electrically connect stacked semiconductor chips, then electrical connection between chips and substrate is achieved, but power consumption increases due to maximum current flow through all chips simultaneously
Solution Approach 1:
The patent segments the electrical connection path by introducing a token ring loop structure that divides the current flow into sequential segments. Instead of all chips receiving power simultaneously through parallel bonding wires, the current flows sequentially through each chip in the stack via the token ring loop, reducing peak current demand and power consumption while maintaining reliable electrical connection.
Solution Approach 2:
The patent introduces an intermediary token ring loop structure between the bonding wires and the semiconductor chips. This intermediary controls and regulates the current flow distribution, preventing maximum current from flowing through all chips simultaneously while ensuring each chip receives necessary power, thus reducing overall power consumption without compromising connection reliability.
2Reliability
If semiconductor chips are vertically stacked to expose bonding pads for wire bonding, then electrical connection is enabled, but device complexity increases due to step structure and multiple bonding processes
Solution Approach 1:
The patent merges the bonding pad exposure requirement with the chip stacking structure by implementing the token ring loop that utilizes the vertical stack configuration. Instead of treating the step structure as a separate complexity issue, the design integrates the token ring loop to flow through the stacked chips, combining the structural arrangement with the electrical connection scheme and reducing overall system complexity.
Solution Approach 2:
The patent makes the bonding pads serve multiple functions: they are used for both the traditional wire bonding connections and as part of the token ring loop structure. This multi-functionality reduces the need for additional structures or processes, simplifying the overall device while maintaining reliable electrical connection through the stacked chips.
3Reliability
If bonding wires are used to connect bond fingers to bonding pads, then electrical signal transmission is achieved, but current management becomes difficult leading to maximum current issues
Solution Approach 1:
The patent introduces dynamic current management through the token ring loop structure, which enables sequential activation and current flow control through the stacked chips. Instead of static parallel connections where all chips receive maximum current simultaneously, the token ring loop dynamically routes current through individual chips in sequence, making current management easier while maintaining reliable signal transmission.
Solution Approach 2:
The patent implements a feedback mechanism through the token ring loop that monitors and controls current flow through the stacked chips. The loop structure provides a return path that enables current management control, allowing the system to regulate current distribution and prevent maximum current issues while ensuring reliable signal transmission through proper current sequencing.
Data Source
AI summary
Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.