Top-and-Bottom-Gate Circuit for Long Gate Lines

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Solution Overview

Problem

Large-scale display panels face signal decay issues due to long gate line lengths, necessitating improved circuit designs to compensate for gate signal transmission.

Innovation Solution

Employing a gate line driving circuit with a pull-up transistor made of polysilicon for increased current capability and a control transistor with an oxide semiconductor layer to reduce leakage current, along with a stack-up structure of transistors sharing a common gate to optimize circuit layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the gate line length is increased for large-scale panels, then the display area is improved, but signal decay occurs during long distance transmission

Engineering Contradiction:
Improvedisplay areaVSAvoidsignal transmission quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The gate driving circuit is divided into multiple shift register stages (first shift register, second shift register, etc.) that sequentially drive different segments of the gate lines. This segmentation allows the long gate line to be driven in stages, compensating for signal decay over long distances while maintaining large display area coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs transistors with different semiconductor materials (LTPS transistor for pull-up transistor, IGZO transistor for control transistor) with different electrical characteristics. The LTPS transistor provides high current driving capability, while the IGZO transistor provides low leakage current, together resolving the signal decay issue in long gate lines.

Inventive Principle:
Principle #35Parameter changes

2Power

If a transistor with high current capability is used for pull-up, then driving capability is improved, but leakage current increases

Engineering Contradiction:
Improvedriving current capabilityVSAvoidleakage current
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

Different regions of the circuit use transistors with different semiconductor material properties tailored to their specific functional requirements. The pull-up transistor uses LTPS for high current capability, while control transistors use IGZO for low leakage, optimizing each local region for its specific purpose.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The circuit employs a composite approach using two different semiconductor materials (LTPS and IGZO) in different transistor positions. This composite material strategy combines the advantages of both materials: high current capability from LTPS and low leakage from IGZO, resolving the contradiction between driving capability and leakage current.

Inventive Principle:
Principle #40Composite materials

3Area of stationary object

If multiple transistors are placed close together for compact layout, then area is reduced, but voltage variation at control end increases

Engineering Contradiction:
Improvecircuit areaVSAvoidvoltage stability
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The IGZO transistor acts as an intermediary between the control signal source and the LTPS pull-up transistor. Its low leakage current property stabilizes the control voltage, preventing voltage variation even when transistors are closely placed for compact layout.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12417750B2Gate line driving circuit with top gate and bottom gate
Publication Date: 2025.09.16 INNOLUX CORP
  • US12417750B2 patent drawing
  • US12417750B2 patent drawing
  • US12417750B2 patent drawing

AI summary

A circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a first end and a second end. The second transistor has a first end and a second end, wherein the first end of the second transistor is coupled to the first end of the first transistor. The third transistor has a first end and a second end, wherein the second end of the third transistor is coupled to the second end of the second transistor. The fourth transistor has a first end coupled to the second end of the first transistor. The fourth transistor has a bottom gate and an oxide semiconductor layer, and the second transistor has a top gate and a silicon semiconductor layer.