Top electrode interconnect structures
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Solution Overview
Problem
Current methods for forming top electrode interconnections in embedded memory devices like RRAM, PRAM, and MRAM face challenges such as a narrow etch process window, high resistance, and risk of shorting, especially during damascene line etch and via hole patterning, which limits scaling and increases costs.
Innovation Solution
The implementation of a self-aligned via interconnection structure that contacts the top electrode and upper metallization layer, formed using a vertical pillar with a bottom electrode, switching materials, and a masking material, allowing for a wider etch process window and reduced defectivity without the need for extra masking steps or via photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etch is made deeper to improve connection, then the connection resistance decreases, but the risk of shorting to the switching layer increases
Solution Approach 1:
A sacrificial liner layer is introduced as an intermediary between the top electrode and the switching layer. This liner layer acts as a protective mediator during the etch process, allowing the etch to proceed deep enough to achieve low contact resistance while preventing direct contact between the conductive interconnect and the switching layer that would cause shorting. The liner is subsequently removed to complete the via formation.
Solution Approach 2:
The sacrificial liner layer is deposited in advance before the etch process. This preliminary action prepares the structure to withstand the etch process by providing pre-positioned protection exactly where needed, enabling the etch to create the necessary conductive path without risking shorting to underlying layers.
2Manufacturing precision
If the top electrode is made thicker to address etch process challenges, then the etch process window widens, but the need for additional overlay masks increases
Solution Approach 1:
The top electrode structure itself serves a dual function: as the functional electrode and as a self-aligned mask for the via formation process. The via is formed directly through the top electrode using the electrode's own material as the masking layer, eliminating the need for separate overlay masks. This self-service approach simplifies the process while maintaining precise alignment.
3Adaptability or versatility
If via hole patterning is used instead of line etch, then the interconnection flexibility improves, but the top electrode loss during etch increases
Solution Approach 1:
The sacrificial liner layer serves as a protective intermediary during via hole patterning. It allows the via etch to proceed through the top electrode with minimal loss, as the liner protects the electrode material from being removed during the etch process. This enables flexible via hole patterning while minimizing material loss.
4Reliability
If the top electrode is scaled down to reduce resistance, then the interconnect performance improves, but the etch process control becomes more difficult
Solution Approach 1:
The sacrificial liner layer acts as a protective mediator that enables precise etch control on scaled-down structures. By providing a distinct, selectively removable layer, it allows the etch process to be precisely controlled and stopped at the correct depth, even when working with thinner top electrodes. This maintains manufacturing precision while enabling performance improvement through scaling.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.