Top-Gate Array Substrate Self-Aligned Gate Electrode
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Solution Overview
Problem
Conventional gate driver on array (GOA) technology for liquid crystal displays (LCDs) faces challenges in improving the driving ability of thin-film transistors (TFTs) due to non-self-aligned gate electrodes and semiconductor layers, leading to electrical leakage and safety issues, which complicates the manufacturing process and increases costs.
Innovation Solution
The proposed array substrate design incorporates a top-gate structure with shielding patterns and through holes to connect source/drain electrodes to heavy doping zones, allowing for improved charge carrier transportation without the need for additional masks, thus enhancing TFT driving ability while maintaining production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode and semiconductor layer are not self-aligned in the GOA bottom-gate structure, then additional masks are necessary to form the light doping zone, but this increases device complexity and manufacturing difficulty
Solution Approach 1:
The patent merges the gate electrode pattern formation and semiconductor layer pattern formation into a single self-aligned process. The gate electrode structure serves as the alignment reference for the semiconductor layer, eliminating the need for separate masking steps and reducing manufacturing complexity while maintaining precise alignment.
Solution Approach 2:
The gate electrode structure provides self-alignment for the semiconductor layer pattern formation. The semiconductor layer is formed using the gate electrode as a template, where the gate electrode's own structure defines the precise location and shape of the semiconductor region, eliminating external alignment requirements.
2Reliability
If the gate electrode extends to the bottom of the source/drain electrode to improve TFT driving ability, then charge efficiency improves, but overlapping of the gate electrode and light doping zone may cause electrical leakage
Solution Approach 1:
The patent applies different doping concentrations at different locations within the semiconductor layer. The light doping zone is positioned adjacent to the gate electrode with controlled doping concentration, while the heavy doping zone is positioned at the source/drain contact regions. This local differentiation allows the gate electrode to extend to the bottom for improved driving ability while preventing electrical leakage through proper spatial separation and doping control.
Solution Approach 2:
The patent resolves the overlap issue by transitioning from a two-dimensional planar layout to a three-dimensional structure with vertical layering. The gate electrode extends vertically to the bottom of the source/drain electrode, while the light doping zone is positioned in a different vertical plane, eliminating harmful overlap while maintaining electrical isolation.
3Manufacturing precision
If additional masks are used to form the light doping zone, then manufacturing precision can be maintained, but production costs increase
Solution Approach 1:
The gate electrode structure serves as a self-aligned template for forming the semiconductor layer and light doping zone. This self-service approach eliminates the need for additional masking steps while maintaining precise pattern alignment, thereby reducing production complexity and increasing manufacturing efficiency without sacrificing precision.
Data Source
AI summary
An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns. A first through hole and a second through hole are arranged on the array substrate. One of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole. The other one of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole and is insulated from the first shielding pattern. The present invention where the array substrate and the method of forming the array substrate are proposed is related to a top-gate design. The driving ability of the TFT driving circuit still improves without increasing the original processes and production costs.