Top-Gate Bottom-Contact Array Substrate Manufacturing
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Solution Overview
Problem
Existing array substrates with thin film transistors in bottom-gate configurations face challenges such as degraded semiconductor thin film regularity and increased production complexity due to the boundaries of source and drain electrodes affecting carrier transport and requiring multiple photolithography steps, leading to high production costs.
Innovation Solution
Implementing a thin film transistor in a top-gate, bottom-contact configuration with two-layered source and drain electrodes and a simplified manufacturing process using a half-tone or gray-tone mask for patterning, reducing the complexity and cost of production while improving semiconductor thin film regularity and contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin film transistor in bottom-gate, bottom-contact configuration is used, then manufacturing process is simpler, but semiconductor thin film regularity is degraded and device properties are worsened
Solution Approach 1:
The patent inverts the traditional bottom-gate configuration to a top-gate configuration. By placing the gate electrode above the semiconductor thin film instead of below, the gate can control the semiconductor film without being obstructed by source and drain electrode boundaries, thereby maintaining manufacturing simplicity while improving semiconductor thin film regularity and device properties.
2Manufacturing precision
If thin film transistor in bottom-gate, top-contact configuration is used, then semiconductor thin film regularity is improved, but manufacturing process complexity increases and production costs rise
Solution Approach 1:
The patent inverts the bottom-gate configuration to top-gate, which naturally improves semiconductor thin film regularity by allowing uninterrupted deposition. Simultaneously, the inverted configuration simplifies the manufacturing process by enabling source and drain electrodes to be formed before the gate electrode, reducing the number of photolithography and masking steps required.
3Manufacturing precision
If multiple photolithography and masking steps are performed, then fabrication precision is improved, but production time increases and productivity decreases
Solution Approach 1:
The patent merges multiple photolithography and masking steps into fewer integrated processes. By reordering the fabrication sequence and using the top-gate configuration, patterns for source, drain, and gate electrodes can be formed with reduced steps, maintaining fabrication precision while significantly improving production efficiency and reducing costs.
Data Source
AI summary
According to embodiments of the present invention, there are provided an array substrate, a method for manufacturing the same and a display device, capable of reducing production difficulty of the array substrate. The manufacturing process of the array substrate is simplified, and the production cost is reduced. The array substrate comprises thin film transistor in a top-gate, bottom-contact configuration which is located on a substrate. Regarding the thin film transistor, its gate electrode is connected to a gate line, its source electrode is connected to a data line, and its drain electrode is connected to a pixel electrode.