Top-Gate Oxide Semiconductor Transistor for Display Signal Delay
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Solution Overview
Problem
As display devices with larger screen sizes and higher resolutions are developed, bottom-gate transistors face issues with signal delay due to parasitic capacitance, leading to degraded image quality, necessitating a top-gate transistor with stable semiconductor characteristics and high reliability.
Innovation Solution
A semiconductor device with a top-gate structure featuring an oxide semiconductor film, where the oxide semiconductor film includes a channel region overlapping with a second gate electrode, and source and drain regions in contact with insulating films, with a specific atomic ratio of In, M (Al, Ga, Y, or Sn), and Zn, and a difference in field-effect mobility less than or equal to 15 cm2/Vs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom-gate transistor structure is used, then the manufacturing process is simple and manufacturing cost is low, but signal delay due to parasitic capacitance becomes severe as screen size increases or resolution increases
Solution Approach 1:
The patent inverts the conventional bottom-gate structure to a top-gate structure, where the gate electrode is positioned above the oxide semiconductor film rather than below it. This inversion changes the capacitance coupling relationship, reducing parasitic capacitance between the gate and source/drain electrodes, thereby solving the signal delay problem in high-resolution display devices while maintaining manufacturing feasibility
2Measurement precision
If the screen size of display device increases or resolution increases, then display quality improves, but signal delay due to parasitic capacitance becomes more severe
Solution Approach 1:
By inverting to a top-gate structure, the patent reduces parasitic capacitance effects that scale with device size and density, enabling high-resolution displays (4K×2K, 8K×4K) to operate without severe signal delay while maintaining image quality
3Reliability
If a top-gate transistor structure is used, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent specifies precise compositional parameters for the oxide semiconductor film (In-Ga-Zn-O with atomic ratios of In:Ga:Zn=4:2:3) and layer thicknesses to optimize electrical characteristics while maintaining manufacturability. These parameter specifications enable consistent top-gate transistor fabrication with reduced parasitic capacitance
Data Source
AI summary
In a transistor including an oxide semiconductor, a variation in electrical characteristics is suppressed and reliability is improved. A semiconductor device includes a transistor. The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, a second gate electrode over the second insulating film, and a third insulating film over the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the second gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. A difference between a minimum value and a maximum value of the field-effect mobility in the case where the field-effect mobility in a saturation region of the transistor is measured.