Top-Gate Oxide Semiconductor Transistors for Low-Delay Displays
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance, leading to degraded image quality, especially in larger or high-resolution displays, and occupy more space compared to planar transistors, necessitating a semiconductor device with stable semiconductor characteristics, high reliability, and a simple manufacturing process.
Innovation Solution
A planar type semiconductor device with transistors having a top-gate structure, where impurity elements like hydrogen, boron, or rare gases are introduced in regions not overlapping with the gate electrode, forming low-resistance regions in contact with hydrogen-containing films, reducing parasitic resistance and capacitance, and using multilayer films with different atomic ratios of metal elements in the oxide semiconductor films for the driver and pixel portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor is used, then the manufacturing process is simple and cost is low, but signal delay increases due to parasitic capacitance
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode at the top instead of the bottom, transforming an inverted staggered structure into a planar structure. This inversion reduces parasitic capacitance between the gate and source/drain electrodes, thereby reducing signal delay while maintaining manufacturing simplicity through sputtering processes
2Ease of manufacture
If an inverted staggered transistor is used, then manufacturing cost is low, but occupation area increases
Solution Approach 1:
By inverting the transistor structure from inverted staggered to planar configuration, the patent achieves more compact layout. The planar structure allows for smaller occupation area compared to the inverted staggered structure, while manufacturing cost remains low due to the use of sputtering processes for forming the oxide semiconductor film
3Area of stationary object
If a planar transistor is used, then occupation area is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the structural parameters of the transistor from inverted staggered to planar configuration. This parameter change reduces occupation area while the manufacturing process remains relatively simple, utilizing standard sputtering techniques to form the oxide semiconductor film, thus avoiding excessive complexity
4Power
If impurity elements are introduced in regions not overlapping with the gate electrode, then on-state current increases, but parasitic resistance must be reduced
Solution Approach 1:
The patent applies local quality by introducing impurity elements (such as hydrogen, boron, or rare gases) specifically in regions of the oxide semiconductor film that do not overlap with the gate electrode. This localized impurity introduction creates low-resistance regions that reduce parasitic resistance, while the overall structure maintains high on-state current through improved carrier concentration in specific areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a semiconductor device with high on-state current, low off-state current, stable electrical characteristics, and a smaller area occupation, enhancing display device performance and reliability while reducing signal delay and parasitic capacitance.
Implementation Method 1
an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions
Implementation Method 2
an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions
Implementation Method 3
The regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen
Data Source
AI summary
A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.