Top Gate Semiconductor Substrate for Display Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In display devices with a touch sensor, the bottom gate TFT structure leads to parasitic capacitance between gate and source electrodes, causing signal dullness due to overlapping electrodes, which results in longer writing times.
Innovation Solution
A semiconductor substrate design featuring a top gate structure where the gate electrode overlaps only the semiconductor film and not the source or drain electrodes, with a light-shielding film to prevent light exposure and a passivation film with high hydrogen concentration to enhance semiconductor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom gate TFT structure is used, then the device can be manufactured with simpler process steps, but parasitic capacitance is generated between gate electrodes and source electrodes due to overlapping arrangement
Solution Approach 1:
The patent inverts the conventional bottom gate structure to a top gate structure, where the gate electrode is positioned above the semiconductor film rather than below it. This inversion allows the gate electrode to overlap with the semiconductor film for effective control while avoiding overlap with source and drain electrodes, thereby eliminating parasitic capacitance and improving signal accuracy.
2Device complexity
If gate electrodes and source electrodes are arranged to overlap in plan view, then the bottom gate structure is achieved, but writing time increases due to parasitic capacitance
Solution Approach 1:
By inverting the gate position from bottom to top, the patent achieves a structure where the gate electrode does not overlap with source and drain electrodes in plan view. This eliminates parasitic capacitance effects, enabling faster signal writing without increasing device complexity.
3Loss of time
If a top gate structure is implemented, then parasitic capacitance is suppressed and writing time is reduced, but the device requires additional insulating film layers
Solution Approach 1:
The patent implements a multi-layer insulating film structure where each layer serves multiple functions: the first insulating film acts as both a barrier layer and part of the gate insulating structure, the second insulating film provides both electrical isolation and mechanical support, and the third insulating film serves as both a protective layer and a planarization layer. This multi-functionality approach manages the increased layer complexity efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses parasitic capacitance, reduces writing time, and improves signal accuracy and efficiency by preventing electrode overlap and enhancing semiconductor conductivity.
Implementation Method 1
a light-shielding film provided on the substrate; a semiconductor film provided on the first insulating film so as to overlap with the light-shielding film when viewed in a plan view
Implementation Method 2
The configuration in which the gate electrodes and the source electrodes overlap with each other, respectively, when viewed in a plan view causes parasitic capacitances to be generated between the gate electrodes and the source electrodes, respectively, which can cause signals to become dull when the signals are written
Data Source
AI summary
A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.