Top Gate Electrode in Thin Film Transistor for Aperture Ratio
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Solution Overview
Problem
The increase in size of thin film transistors in display panels leads to a larger bezel area and reduced aperture ratios, necessitating a method to enhance driving performance without increasing transistor size.
Innovation Solution
Implementing a thin film transistor structure with a planarization layer between the second gate electrode and semiconductor layer, where the second gate electrode is electrically connected or insulated from the first gate electrode, and using a top gate electrode configuration to reduce the transistor's footprint while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of thin film transistor is increased to enhance driving performance, then the current characteristics are improved, but the bezel area increases and aperture ratios are reduced
Solution Approach 1:
The patent introduces a dual-gate transistor structure where a second gate electrode is added above the semiconductor layer, utilizing the vertical dimension to enhance driving performance without increasing the horizontal footprint of the transistor. This allows improved current characteristics while maintaining compact device area and aperture ratios.
Solution Approach 2:
The second gate electrode is positioned within the vertical stack of the transistor structure, nested between the semiconductor layer and the planarization layer. This nesting approach allows the additional functional element (second gate) to be integrated without increasing the overall device footprint, thereby improving performance while maintaining compact area.
2Reliability
If the size of thin film transistor is increased to enhance driving performance, then the current characteristics are improved, but the aperture ratios are reduced
Solution Approach 1:
The patent introduces a dual-gate transistor structure where a second gate electrode is added above the semiconductor layer, utilizing the vertical dimension to enhance driving performance without increasing the horizontal footprint of the transistor. This allows improved current characteristics while maintaining compact device area and aperture ratios.
3Stability of the object's composition
If a planarization layer is disposed on the thin film transistor, then the structural integrity is improved, but the transistor area increases
Solution Approach 1:
The planarization layer is selectively disposed only in regions where it is needed for structural support and electrical connection, rather than covering the entire transistor area. Specifically, it is positioned to support the second gate electrode and provide contact holes for electrical connections, while leaving the channel region exposed to maintain small transistor footprint.
Data Source
AI summary
Embodiments of the disclosure are related to display devices, a planarization layer disposed on a thin film transistor in a display panel is removed to form an opening in the planarization layer, and a top gate electrode is disposed in the opening of the planarization layer, thus a driving performance of the thin film transistor is enhanced while reducing a size of the thin film transistor disposed in the display panel. Furthermore, the top gate electrode is implemented using an electrode layer located on an upper layer of the planarization layer, the thin film transistor including double gate electrodes is implemented easily without an additional process.