Top-Gate TFT Gate Insulation Profile for Stable Channel Length
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Solution Overview
Problem
In the manufacturing of OLED display substrates, forming an ideal morphology of the gate insulation layer is challenging, leading to short channel regions under the gate insulation layer, which affects the threshold voltage characteristic and product quality of Thin Film Transistors (TFTs).
Innovation Solution
A manufacturing method for a top-gate type thin film transistor on a display substrate involves forming a gate insulation layer with a specific thickness and slope angle using a gaseous corrosion method, ensuring the active layer is partially exposed and conductively treated, and connecting source and drain electrodes through via holes, while incorporating a light shielding layer and multiple insulation layers to improve TFT performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form the gate insulation layer, then the manufacturing process is simple, but the morphology of the gate insulation layer is poor and etching residue remains
Solution Approach 1:
The patent changes the etching parameters by introducing a gaseous corrosion method with specific gas composition (CF4 and O2) and flow rates. This transforms the etching process from a simple liquid or plasma spray method to a controlled gaseous corrosion process that achieves superior morphology without excessive complexity
Solution Approach 2:
The patent employs gaseous corrosion using CF4 and O2 gases to etch the gate insulation layer. This pneumatic approach replaces conventional liquid or plasma methods, achieving clean etching with good morphology and no residue while maintaining process feasibility
2Speed
If the gate insulation layer is made thinner to reduce capacitance, then the switching speed improves, but the etching becomes more difficult and morphology control becomes harder
Solution Approach 1:
The patent optimizes the gate insulation layer thickness to 0.1-0.2 μm and adjusts the gaseous corrosion parameters (gas flow rates, temperature, pressure) to achieve precise etching at this thin dimension. The specific parameter combinations enable both thin layer processing and high etching precision
Solution Approach 2:
The patent implements process monitoring and control during the gaseous corrosion etching process to maintain precise morphology control. By monitoring etching progress and adjusting gas flow rates dynamically, the system achieves consistent results at thin thicknesses while preventing etching residue
3Reliability
If the channel region length is increased to improve threshold voltage control, then the TFT performance improves, but the device area increases
Solution Approach 1:
The patent uses a thin gate insulation layer (0.1-0.2 μm) that allows for extended channel length without proportionally increasing device area. The thin film structure enables better electric field control along the extended channel, improving threshold voltage characteristics while minimizing area penalty
Solution Approach 2:
The patent optimizes the vertical structure with multiple layers (gate electrode, gate insulation layer, active layer with specific morphology) to achieve better threshold voltage control through improved electric field distribution. This dimensional optimization allows extended channel length effects without linear area increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures a good morphology of the gate insulation layer, preventing etching residue and maintaining the channel region length, thereby enhancing the threshold voltage characteristic and overall product quality of the display device.
Implementation Method 1
over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer
Data Source
AI summary
Provided are a manufacturing method of a display substrate, a display substrate, and a display device. The display substrate includes: a base substrate; and a top-gate type thin film transistor located on a side of the base substrate, the top-gate type thin film transistor comprises an active layer, a gate insulation layer and a gate electrode sequentially disposed in a direction away from the base substrate. A side surface of the gate insulation layer close to the gate electrode extends beyond an edge of the gate electrode in a direction parallel to the base substrate, and a side surface of the active layer close to the gate insulation layer extends beyond an edge of the gate insulation layer in the direction parallel to the base substrate.