Top-Gate TFTs Using Digital Lithography Masks
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Solution Overview
Problem
Current methods for manufacturing thin-film transistors on transparent substrates face challenges in reducing feature size and minimizing parasitic capacitance due to large droplet sizes in phase-change material deposition and the high costs associated with traditional photolithography, which limits the production of high-performance devices with smaller channel lengths.
Innovation Solution
The use of digital lithography systems, such as ink-jet and ballistic aerosol marking, to deposit phase-change masking materials in a patterned form, allowing for self-aligned channel and gate electrode formation without the need for elaborate alignment tools, enabling the creation of transistors with channel widths as small as 5-15 microns by forming channels in the interstices between masking elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If phase-change material droplets are used for masking, then manufacturing cost is reduced, but feature size becomes too large (20-40 microns) for high-performance devices
Solution Approach 1:
The patent divides the masking function into two separate steps: first depositing phase-change material droplets as coarse masks, then applying a second photolithographic mask for precise feature definition. This segmentation allows each process to optimize for its strength - droplet deposition for cost reduction and photolithography for precision - while combining their benefits.
Solution Approach 2:
The phase-change material droplets are deposited in advance to create preliminary masks that define the general pattern and provide self-alignment references. This preliminary action establishes the framework upon which the final precise features are formed, reducing the complexity of the subsequent photolithographic alignment.
2Manufacturing precision
If traditional photolithography is used, then alignment precision is improved, but manufacturing cost increases due to expensive alignment tools and chemical treatments
Solution Approach 1:
Instead of using full photolithographic processing for all masking steps, the patent applies photolithography only where precision is absolutely necessary - specifically for the final feature definition and self-alignment. The majority of the patterning is accomplished through the simpler, cheaper phase-change material deposition, reducing overall chemical treatment requirements and costs.
Solution Approach 2:
The patent implements self-aligned patterning where the phase-change material droplets automatically serve as alignment references for subsequent photolithographic steps. The source and drain electrodes formed from the droplet masks automatically align the gate electrode, eliminating the need for expensive external alignment tools and complex alignment procedures.
3Device complexity
If larger droplet sizes are used, then manufacturing simplicity is maintained, but parasitic capacitance increases due to larger channel lengths
Solution Approach 1:
The patent segments the channel length definition into two components: the droplet spacing establishes the general channel region, while the photolithographic mask defines the precise channel boundaries. This allows the channel length to be precisely controlled (5-15 microns) independent of the larger droplet size, reducing parasitic capacitance while maintaining manufacturing simplicity.
Solution Approach 2:
The patent changes the interpretation of how droplet size relates to feature size. Instead of directly using droplet diameter as the feature dimension, the droplets serve as spacing markers, and the actual feature size is defined by the photolithographic pattern between them. This parameter decoupling allows small features with large droplets, reducing parasitic capacitance without sacrificing manufacturing simplicity.
4Manufacturing precision
If self-aligned patterning is implemented, then gate electrode alignment with channel boundaries is improved, but process complexity increases
Solution Approach 1:
The patent implements self-aligned patterning where the source and drain electrodes, formed from the phase-change material droplet masks, automatically serve as the alignment references for the gate electrode photolithography. The gate electrode is aligned to the channel boundaries by using the existing electrode structures as masks, eliminating the need for separate alignment marks or complex alignment procedures. This self-service approach achieves precise alignment while minimizing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by eliminating the need for expensive alignment tools and achieves smaller feature sizes, improving device performance by minimizing parasitic capacitance and aligning the gate electrode with the channel boundaries, resulting in high-performance thin-film transistors comparable to traditional bottom gate devices.
Implementation Method 1
a suitable material, such as a stearyl erucamide wax, is maintained in liquid phase over an ink-jet style piezoelectric printhead, and selectively ejected on a droplet-by-droplet basis such that droplets of the wax are deposited in desired locations in a desired pattern on a layer formed over a substrate. The droplets exit the printhead in liquid form, then solidify after impacting the layer
Implementation Method 2
The photoresistive materials are exposed through a mask, developed to remove portions of the materials
Data Source
AI summary
A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.