Top-Gate Thin-Film Transistor Layout for Uniform Electric Field
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Solution Overview
Problem
Existing thin-film transistors in electronic displays face issues with durability and performance due to atmospheric sensitivity of semiconductor materials and manufacturing tolerances, leading to non-uniformity and reduced reliability.
Innovation Solution
The design incorporates a top gate structure with a nonconductive substrate, a semiconductor layer, source and drain electrodes that do not overlap the etch stop layer, and a gate electrode, using materials like indium gallium zinc oxide and conductive materials, with a method involving deposition and etching processes to form precise electrode positions, ensuring the semiconductor layer is protected and uniformly influenced by the electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom gate structure is used with conventional manufacturing processes, then the manufacturing process is simpler, but the transistor durability and performance are reduced due to atmospheric sensitivity of semiconductor materials
Solution Approach 1:
The patent inverts the conventional bottom gate structure to a top gate structure, where the gate electrode is positioned above the semiconductor layer rather than below. This inversion allows the gate to better protect the semiconductor layer from atmospheric exposure during manufacturing and operation, thereby improving durability and performance while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies a protective coating to the semiconductor layer before completing the manufacturing process. This preliminary protective action prevents atmospheric degradation of the semiconductor materials during subsequent manufacturing steps and device operation, addressing the atmospheric sensitivity issue without requiring complete process redesign
2Productivity
If conventional etching processes are used without precise control, then the manufacturing process is faster, but manufacturing precision and transistor uniformity are reduced
Solution Approach 1:
The patent replaces conventional mechanical etching processes with a self-aligned deposition process. Instead of using mechanical etching tools that require precise positioning, the source and drain electrodes are formed by depositing conductive material that automatically aligns with the semiconductor layer features, eliminating positioning errors and improving manufacturing precision while maintaining productivity
Solution Approach 2:
The patent implements a self-aligned manufacturing approach where the electrode patterns automatically align with the semiconductor layer features during deposition. This self-service mechanism eliminates the need for complex alignment procedures and precise mechanical positioning, thereby improving both manufacturing precision and efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the durability and performance of thin-film transistors by protecting the semiconductor layer from atmospheric degradation and improving manufacturing precision, resulting in more stable, reliable, and uniform transistors with increased durability compared to bottom gate designs.
Implementation Method 1
an entire area of the semiconductor layer underlying the etch stop layer can be influenced by a field from the gate electrode
Implementation Method 2
The thin-film transistors are generally formed by depositing films of certain materials on a substrate
Implementation Method 3
selectively removing parts of the films by etching or other processes to form transistors
Data Source
AI summary
The present disclosure is drawn to thin-film transistors, electronic displays that include thin-film transistors, and methods of making thin-film transistors. In one example, a thin-film transistor can include a nonconductive substrate, a semiconductor layer on the nonconductive substrate, a source electrode adjacent a first side of the semiconductor layer and partially overlapping a first peripheral portion of the semiconductor layer, a drain electrode adjacent a second side of the semiconductor layer and partially overlapping a second peripheral portion of the semiconductor layer, an etch stop layer on the semiconductor layer, a gat insulator layer on the etch stop layer, and a gate electrode on the gate insulator layer. The source electrode and the drain electrode do not overlap the etch stop layer.