Top-Gate TFT Structure With MoS2 Protection for LCD Scaling

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Solution Overview

Problem

Current methods for fabricating thin film transistors (TFTs) on flexible substrates face challenges due to the sensitivity of semiconductor materials like MoS2 to oxygen plasma patterning, limiting the production of high-speed, low-power transistors for flexible electronics, and existing TFTs on glass substrates are not scalable for liquid crystal displays (LCDs).

Innovation Solution

A method involving a top-gate TFT structure with a process-sensitive semiconductor active layer protected by an active layer protection film, which is patterned using oxygen plasma-resistant materials like Al2O3, allowing for the formation of multiple TFTs on a glass substrate and integration into LCDs, using materials such as MoS2 or organic semiconductors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If oxygen plasma patterning is used to fabricate MoS2 TFTs, then device performance can be achieved, but the MoS2 semiconductor layer is damaged and production is limited to one device at a time

Engineering Contradiction:
Improvedevice performanceVSAvoidproduction scalability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A protective film is introduced as an intermediary layer between the oxygen plasma etching process and the MoS2 semiconductor layer. This film allows plasma patterning to proceed without damaging the underlying MoS2, enabling scalable multi-device fabrication while maintaining device performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective film is deposited on the MoS2 layer before the oxygen plasma patterning step. This preliminary protective action prevents plasma-induced damage to the semiconductor layer, allowing subsequent high-speed plasma etching processes to be used for scalable TFT production

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional TFT fabrication methods are used on glass substrates, then manufacturing simplicity is maintained, but high-speed performance and low-power consumption cannot be achieved

Engineering Contradiction:
Improvefabrication simplicityVSAvoidcarrier mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The semiconductor material is changed from conventional amorphous silicon to 2D MoS2, which has fundamentally different electrical properties including much higher carrier mobility (>200 cm²/V·s compared to ≤1 cm²/V·s for amorphous silicon). This material parameter change enables high-speed performance while maintaining compatibility with glass substrate fabrication

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The device structure combines 2D MoS2 semiconductor material with conventional glass substrate and standard TFT architecture. This composite approach integrates the high-performance properties of 2D materials with the manufacturing advantages of conventional glass-based fabrication processes

Inventive Principle:
Principle #40Composite materials

3Speed

If monolayer MoS2 is used for high carrier mobility, then speed performance improves, but the material becomes sensitive to oxygen plasma damage

Engineering Contradiction:
Improvecarrier mobilityVSAvoidplasma sensitivity
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The protective film serves as a mediator that shields the monolayer MoS2 from direct exposure to oxygen plasma. This allows the high-mobility monolayer structure to be processed using plasma-based patterning techniques without suffering plasma-induced damage

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective film is applied to the MoS2 surface before plasma processing. This preliminary protection enables subsequent oxygen plasma etching and cleaning steps to be performed on the device structure without compromising the integrity of the monolayer semiconductor

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance and scalability of TFTs by protecting the semiconductor layer during patterning, reducing voltage thresholds and increasing drain current saturation, enabling the production of high-speed, low-power flexible transistors suitable for LCDs.

Implementation Method 1

Monolayers of MoS2 are sensitive (i.e., prone to damage) to semiconductor device patterning techniques such as oxygen plasma

Methodology Applied
Scientific EffectOxygen plasma: Plasma

Implementation Method 2

a gate dielectric layer disposed over the active layer protection film

Methodology Applied
Scientific EffectDielectric insulation: Dielectric

Data Source

PatentUS12013619B2Methods for forming thin film transistors on a glass substrate and liquid crystal displays formed therefrom
Publication Date: 2024.06.18 CORNING INC
  • US12013619B2 patent drawing
  • US12013619B2 patent drawing
  • US12013619B2 patent drawing

AI summary

A thin film transistor (TFT) liquid crystal display (LCD) comprises a plurality of image pixels demarcated between an overlying liquid crystal display layer and an underlying glass substrate. Each image pixel comprises a dedicated top-gate TFT disposed over the glass substrate. Each top-gate thin film transistor comprises a process sensitive semiconductor layer disposed over the glass substrate, and a source electrode and a drain electrode disposed over the process sensitive semiconductor layer. The process sensitive semiconductor layer forms a process sensitive semiconductor active layer between the source electrode and the drain electrode and an active layer protection film is disposed over the process sensitive semiconductor active layer. A gate dielectric layer is disposed over the active layer protection film between the source electrode and the drain electrode and a gate electrode is disposed over the gate dielectric layer.